Digital Microelectronic Circuits ( ) The CMOS Inverter. Lecture 4: Presented by: Adam Teman


 Vanessa Cameron
 2 years ago
 Views:
Transcription
1 Digital Microelectronic Circuits ( ) Presented by: Adam Teman Lecture 4: The CMOS Inverter 1
2 Last Lectures Moore s Law Terminology» Static Properties» Dynamic Properties» Power The MOSFET Transistor» Shockley Model» Channel Length Modulation, Velocity Saturation, Body Effect
3 This Week  Motivation The Inverter, or NOT gate, is truly the nucleus of all digital designs. We will analyze the inverter and find its characterizing parameters. Once its operation and properties are clearly understood, designing and analyzing more intricate structures, such as NAND gates, adders, multipliers and microprocessors is greatly simplified. This lecture focuses on the static CMOS inverter the most popular at present and the basis for the CMOS digital logic family. In In Out Out 3
4 What will we learn today? 4.1 An Intuitive Explanation 4. Static Operation 4.3 Dynamic Operation 4.4 Power Consumption 4..1 The Inverter s VTC 4.. Operating Regions 4..3 Switching Threshold 4..4 Noise Margins Parasitic Capacitances 4.3. Propagation Delay Device Sizing  β Device Sizing S Sizing a Chain of Inverters Dynamic Power 4.4. Short Circuit Power Static Power Total Power Consumption 4.5 Summary 4
5 An Intuitive Explanation 4. Static Operation 4.3 Dynamic Operation 4.4 Power Consumption 4.5 Summary As usual, we ll start with AN INTUITIVE EXPLANATION 5
6 An Intuitive Explanation A Static CMOS Inverter is modeled on the double switch model. The basic assumption is that the switches are Complementary, i.e. when one is on, the other is off. When the top switch is on, the supply voltage propagates to the output node. When the bottom switch is on, the ground voltage is propagated out. V +  V0 6
7 An Intuitive Explanation Now we will replace the model switches with real voltage controlled switches MOS Transistors. We will use complementary transistors one nmos and one pmos, and hook them up to the same input voltage. Now, when we set a high input voltage, the nmos is on and the pmos off. The ground voltage propagates. When we put a low input voltage, the pmos is on and the nmos is off. The supply voltage propagates. We ve built an inverter! V V in =V =0 +  V out =0 V out =V in 7
8 An Intuitive Explanation The voltage connected to the Source of the pmos is known as the Supply Voltage or V DD.* We mark the connection to V DD with a horizontal or slanted bar. Accordingly, V DD represents a logical 1 and GND represents a logical 0. Inputting V DD to the CMOS inverter will present GND at the output. Inputting GND will present V DD at the output. This characteristic is nontrivial and is one of the advantages of CMOS design. It is known as Rail to Rail Swing.** * It can also be called V CC, regarding the Collector of BJT transistors. ** Rails are the supply voltages, i.e. V DD and GND. If a voltage is connected to the nmos Source instead of GND, we refer to this voltage as V SS. 8
9 An Intuitive Explanation 4. Static Operation 4.3 Dynamic Operation 4.4 Power Consumption 4.5 Summary Now that we understand the principles, we ll analyze STATIC OPERATION 9
10 Reminder: The Unified MOSFET Model W V n DSeff I k V V V 1 V Ln V min V V, V, V DSn n GSn Tn DSeff n DSn DSeff GSn Tn DSn DSATn 10
11 Reminder: Static Properties VTC Noise Margins 11
12 The Inverter s VTC To construct the VTC of the CMOS inverter, we need to graphically superimpose the IV curves of the nmos and pmos onto a common coordinate set. We can see that: I V V SDp GSn DSn I DSn V V V Vin SGp DD in V V V Vout SDp DD out V in V SGp V GSn V SDp I SDp V DD V out I V DSn DSn 1
13 The Inverter s VTC Since V in and V out are the input and output voltages of the nmos transistor, we will change the coordinates of the pmos. I SDp DSn V V V out DD SDp V V V I in DD SGp DSn I SDp V in =0 V in =1.5 V SGp =.5 V SGp =1 V out SDp For V DD =.5V 13
14 The Inverter s VTC The Now, intersection we will superimpose of corresponding the modified load pmos lines shows IV curves the DC on operating the nmos points, IV graphs: where the currents of the nmos and pmos are equal. I DSn V in =0 V in =V DD V in =V DD / V in =V DD / V in =V DD V in =0 V out 14
15 The Inverter s VTC Putting all the intersection points on a graph with the corresponding output voltage will give us the CMOS inverter s VTC: V out V DD V DD / V DD / V DD V in 15
16 Intuitive Operating Regions V out V DD V DD / V DD / V DD V in 16
17 Operating Regions Let s figure out what region of operation each transistor is in throughout the VTC curve.* * Considering Long Channel Transistors With V T <V DD / V DD Vout V out V in V VGSn Vin VT Cutoff T V SGp V SDp V DD / VSGp VDD Vin VT VSDp VDD Vout VSGp VT Linear V GSn V T V DD / V DD V in 17
18 Operating Regions So now, let s jump to the other side of the VTC. V out V V V in DD T V DD VSGp VDD Vin VT Cutoff V SGp V DD / VGSn Vin VDD VT VT VDSn Vout VGSn VT Linear V DSn V GSn V out V DD / V DD V T V DD V in 18
19 Operating Regions Now, back to the VTC regions. Let s see what happens when we raise the input voltage slightly past V T. V DD Vout V out V in V T V SGp V SDp VGSn Vin VT VDSn Vout VDD VGSn VT Sat VSGp VDD Vin VT VSDp VDD Vout 0 VSGp VT Linear V GSn V T +ΔV V DD V in 19
20 Operating Regions The same when V in is a bit more than V T lower than V DD. V out V V V V in DD T V DD V SGp V SDp VSGp VDD Vin VT VSDp VDD Vout VDD VSGp VT Sat VGSn Vin VT VDSn Vout 0 VGSn VT Linear V GSn V out V DD V T ΔV V DD V in 0
21 Operating Regions Finally, we have the middle area, where: V out V DD V V V in DD VSGp VDD Vin VDD VT Sat VSDp VDD Vout VDD VSGp VT V SGp V SDp VGSn Vin VDD VT VDSn Vout VDD VGSn VT V out Sat V GSn V DD / V DD V in 1
22 Operating Regions To Sum it up: V DD V out nmos off pmos  res nmos sat pmos  res nmos sat pmos  sat nmos res pmos  sat Towards the rails, one of the transistors is cut off, and the other is resistive. Once the cut off transistor starts conducting, it immediately is saturated. As we approach the middle input voltages, both transistors are saturated. The VTC slope is known as the Gain of the gate. nmos res pmos  off V DD V in
23 Switching Threshold The Switching Threshold, V M, is the point where V in =V out. This can be calculated:» Graphically, at the intersection of the VTC with V in =V out V out V DD V M» Or analytically, by equating the nmos and pmos saturation currents with V in =V out. V DD V in 3
24 Switching Threshold But let s start with the intuitive approach 4
25 Switching Threshold Let s analytically compute V M.» Remember, the saturation current for a MOSFET is given by:» Lets assume λ=0 and we ll equate the two currents:» Now we ll substitute: I k V V V 1 DS GS T DS k k n I V V V V p D GSn Tn SGp Tp VGSn Vin V V M SGp VDD Vin VDD VM» And we ll arrive at: V M V r V V 1 r Tn DD Tp r k k p n 5
26 Switching Threshold As we can see, r is an important factor in setting the switching threshold. r is a design parameter, that is set by the drive strength ratios of the nmos and pmos: r long _ channel k k p n W k k C L ox W L Using the current equations again, we can find the drive strength ratio for a desired V M : k p VM VTn k V V V n DD M Tp 6
27 Switching Threshold A symmetric VTC (V M =V DD /) is often desired. In this case: V M V V r V V DD 1 r Tn DD Tp W n W L L Generally, the same length (L min ) is taken for all transistors in digital circuits, and so for a symmetric VTC: p p n W W p n n p...4 7
28 Reminder: Noise Margins V OHmax V OHmin V DD NM V V H OH min IH NM H V IH V OLmax NM L V IL V OLmin GND NM V V L IL OL max NM min NM, NM L H 8
29 Noise Margins One of the CMOS logic family s advantages is a Full Rail to Rail Swing. In other words: V V OH max OLmin To calculate the Noise Margins, we will need to find V IL and V IH. These are the points where the gain is 1. V V out DD GND To do this we will equate the currents:» V IL nmos sat, pmos res» V IH nmos res, pmos sat V DD V DD V in 9
30 Noise Margins Let s calculate V IH : V k I res k V V V I sat V V Assuming matching devices (k n =k p, V Tn =V Tp ): Differentiating and equating 1, we reach: DSn p DSn n GSn Tn DSn DSp GSp Tp V 1 out V V V V V V IN T out DD IN T 1 V 5 V V 8 IH DD T Doing the same for V IL or using symmetry, we reach: 1 V 3 V V 8 IL DD T Accordingly, for a matched longchannel device, and assuming V OHmin V OHmax and V OLmax V OLmin in CMOS, we get: 1 NM NM V V V 0 3V V H L DD IH IL DD T Digital Microelectronic Circuits The VLSI Systems Center  BGU Lecture 8 4: The CMOS Inverter 30
31 Noise Margins The previous analysis assumed many things and therefore SHOULD NOT be memorized. Let us look at the noise margins intuitively to try and understand trade offs: 31
32 Summary of Static Properties When Vin<VT or Vin>VDDVT, one of the networks (PUN/PDN) is off, providing Rail to Rail Swing. The skew of the VTC is set by the sizing ratio between the PUN and PDN. Analytic Noise Margin calculation is rigorous and approximation should be used when possible. 3
33 An Intuitive Explanation 4. Static Operation 4.3 Dynamic Operation 4.4 Power Consumption 4.5 Summary Now that we see how the inverter behaves in steady state, we will analyze it s transient: DYNAMIC OPERATION 33
34 Reminder: Dynamic Properties Propagation Delay Rise/Fall Time 34
35 Parasitic Capacitances Remember that our transistors have capacitance connected to the output node. We ll calculate the capacitance values in the next lecture, but for now, let s just use and equivalent output capacitance. When the input is low our pmos is a nonlinear resistor and our nmos is cut off, so we get a simple RC circuit. Our capacitance is charged, bringing the output voltage to V DD. V +  V DD C eq 35
36 Parasitic Capacitances When the input is high, we essentially have closed the top switch and opened the bottom one. This creates a resistive path from the capacitor to GND, and blocks the path from the supply to the output. Again we have an RC network, though this time we are just discharging the capacitance to GND. We end up with an output equal to GND. 0 C eq 36
37 Parasitic Capacitances So we saw that, a switching CMOS inverter charges and discharges a parasitic output capacitance. During the switching process, we can create a model that will transform the circuit into a simple RC network. In this way, we can easily derive a first order analysis of the CMOS dynamic operation for propagation delay and power consumption calculation. 37
38 Parasitic Capacitances For now, let us make the following assumptions:» A transistor has a gate capacitance that is proportional to its area (W*L)» A transistor has a diffusion capacitance that is proportional to its width (W) 38
39 Parasitic Capacitances For now we will use a very simple model to represent all the parasitic capacitances between the output node and ground. Driver C C C N C load out wire in Load C wire C out,1 C in, C int C ext 39
40 Propagation Delay Using our simple model for load capacitance, we can write: Assuming an ideal step at the input, the propagation delay, t pd is the time it takes the output to (dis)charge 50% of its voltage. We will look at three ways to calculate the propagation delay:» By solving the integral above.» By approximating the average current» By using equivalent resistance t t dt v v 1 1 C load i v v out out dv out 40
41 t pd solving the integral We ll start with V in =0. Accordingly, P1 is open and N1 is closed, causing the output voltage to be held at V out =V DD At t=0, V in changes from 0 to V DD, closing P1 and opening N1. This causes the output to discharge like a first order RC network. V in V DD V out t=0 t C eq V DD t 41
42 t pd solving the integral At this point V DSn =V DD >V GS V T, so N1 is in saturation and the discharge current is given by: n I k V V V 1 DSn In T out V DD V DD V T Assuming λ=0 and integrating until N1 enters the linear region: V out DD T C C V V V load t p1 dv VDD i kn D sat VDD VT V V DD DD T V DD / t p1 t phl t 4
43 t pd solving the integral Now V DSn <V GS V T and so N1 goes into linear operation with: V I DSn res kn Vin VT Vout We ll write an expression for the change in voltage: out V DD V DD V T V DD / And arrive at the following integral: V out t p dv i dt k V V V V t phl DSn n out out in T out Cload Cload dt Cload k V V V DD t1 VDD V n DD T T V dvout 1 V V DD T out V out t p1 t p t phl t 43
44 Using the equality: We get: t p dx 1 ln1 ax x ax t pd solving the integral C load 3VDD 4V T ln kn VDD And putting together the two parts, we get: For V T =0.V DD, we get: V DD V DD V T V DD / V out C load V 1 T 3V 4 1 ln DD V T t phl t p t p kn VDD VT VDD VT VDD t t p t p1 t phl phl 1.6C load kv n DD t p Cload k V V n DD T V V DD DD V TH V DD dvout 1 V V T out V out t 44
45 t pd average currents Instead of solving the integral, we can sometimes assume a linear change in current to make life much easier. This assumption just lets us find the average current between t=0 and t=t phl and calculate: t phl C i load V DSn avg 1 C load V DD 0 i i t DSn DSn phl 45
46 Example t pd average current» Step input into a CMOS inverter with a minimum sized nmos driving a 1.5fF load. t 0» VDS=VDD, VGSVT=VDDVT t pd min,, V V V V V V DSeff DD DD Tn DSatn DSat I DS t0 k n VGTnVDSatn 0.5V DSatn 1 VDSn A 0.18» VDS=VDD/, VGSVT=VDDVT min,, V V V V V V DSeff DD DD Tn DSatn DSat I DS t0 kn VGTnVDSatn VDSatn VDSn A
47 t pd average current» The average current is: I Avg 0.5 I DS t0 I DS t pd 8.65 A» So we can find the delay: V t V t0 pd 0.9 t pd CL 1.5 f 16.33ps I 8.65 Avg 47
48 t pd equivalent resistance A good way to estimate the propagation delay is by finding the resistance of the MOSFET during the transition and using this resistance in quick calculations. The primary approach to deriving such an equivalent resistance is to calculate the transistor s average resistance throughout its operation (ON) period. t t 1 1 VDS t Req averaget t 1... t R on t Ron t dt dt t t t t I t 1 t 1 t DS R on t R t 1 on 48
49 t pd equivalent resistance Now, we will calculate the propagation delay of a short channel inverter, by using the equivalent resistance to discharge a capacitor from V DD to V DD /. Assuming V DD >>V DSATn, we can assume that throughout the propagation delay, the transistor is velocity saturated. We can write: VDD 1 VDS 3 VDD 7 eq DS 1 DD V / DD I / DSAT 1 VDS 4 I DSAT 9 V R dv V DD V I DSAT kn VDD VT VDSAT DSAT 49
50 t pd equivalent resistance For example, if VDD=1.8V: I DSATn k n VGTnVDSatn 0.5V DSatn A VDD 7 Reqn 1 VDD 4 I 9 DSAT k A 9 50
51 t pd equivalent resistance So all we need is to use our magic equation: t 0.69R C k 1.5 f 16.75ps pdhl eqn L Remember that for t pd, we also need R eqp for: t pd t plh t 0.69C R R phl load eqp eqn 51
52 t pd equivalent resistance To calculate and analyze the parameters that affect the propagation delay, we will take λ=0 and get: t phl 3 V V C 0.69Cload I DSATn k V V V Accordingly, we can minimize the delay in the following ways:» Minimize C load.» Increase W/L» Increase V DD DD DD load n DSATn DD Tn V DSAT 5
53 Last Lecture CMOS Inverter» Intuitive Explanation» VTC» VM» Noise Margins» Propagation Delay 53
54 Affect of Device Sizing So we saw that to reduce the propagation delay, we need to increase the device sizes (W/L). But how much should we increase them? What are the tradeoffs? For this, we will discuss two sizing parameters:» Beta Ratio (β)» Upsizing Factor (S) 54
55 What happens when we upsize a transistor? Effective resistance decreases: Gate and Drain Capacitance increase: 55
56 Device Sizing  β Device Sizing is the Width to Length ratio (W/L) of the transistor. When discussing a CMOS logic gate, we relate to the pmos/nmos ratio ((W p /L p )/(W n /L n )).» We will call this ratio β. To get a balanced inverter (i.e. V m =V DD /) we usually will need β=33.5, mainly due to the mobility ratio of holes and electrons. This generally equates the propagation delay of HightoLow and LowtoHigh transitions. However, this does not imply that this ratio yields the minimum overall propagation delay. 56
57 Device Sizing  β How can this be?» To get a faster t plh, we need to enlarge the pmos width.» This increases the parasitic capacitance (C load ), degrading t phl. 57
58 Device Sizing  β 58
59 Device Sizing  β We will now find the optimum ratio for sizing an inverter, considering two identical cascaded CMOS inverters. The load capacitance of the driving gate is: C C C C load out1 in wire Assuming the input capacitance is the gate capacitance of the transistors (C g ) and the output capacitance is the drain capacitance (C d ), we can write: Driver C C C C C C C out,1 load dp1 dn1 gp gn wire C int C ext Load C wire C in, Assuming a linear dependence on device size, we get: 1 1 W L W L C C C C load dn gn wire p n 59
60 Device Sizing  β Noting that we have reduced the equivalent resistance of the pmos by β, we can write the first order RC propagation delay: 0.69C Reqp load t pd Reqn Reqp Cdn1 Cgn C wire Reqn Now we just need to find the minimum: dt pd 0 d R eqp C R wire opt 1 R C 1 C R Cdn1Cgn Cwire eqn dn gn eqn A typical optimum for β is usually around. eqp 60
61 Conclusions: Device Sizing  β» A balanced inverter isn t usually the fastest possible inverter.» A typical optimal pmos/nmos ratio for performance is given by: Reqp opt R eqn 61
62 Device Sizing  S We saw how the ratio between the pmos and nmos can be optimized to improve performance. Now, we will take a balanced inverter and see how upsizing affects the intrinsic or unloaded delay. We will start by writing the delay as a function of the intrinsic capacitance (diffusion and overlap) and the extrinsic capacitances (fanout and wiring): C C C load int ext t 0.69R C 0.69R C C pd eq load eq int ext 6
63 Device Sizing  S Now, we will mark the minimal intrinsic delay as t p0. This is the delay of a minimum sized balanced inverter only loaded by its own intrinsic capacitance (C ext =0): tp0 0.69Rref Cref We will now mark the sizing factor, S. This is the relative upsizing of the inverter, i.e. C int =SC ref and accordingly R eq =R ref /S. Now we can write the delay of an upsized inverter: R t 0.69R C C 0.69 SC C S ref int pd eq ext ref ext C ext C ext 0.69Rref Ciref 1 t p0 1 SC ref SC ref 63
64 Device Sizing  S t t C pd p0 1 ext SC ref 64
65 Conclusions: Device Sizing  S t t C pd p0 1 ext SC ref» The intrinsic delay of an inverter (t p0 ) is independent of the sizing of the gate and is purely determined by technology. When no load is present, an increase in the drive of the gate is totally offset by the increased capacitance.» To minimize a loaded inverter s delay, S should be enlarged, but at the expense of a substantial gain in area. 65
66 Summary of Dynamic Parameters We can calculate t pd in several ways, but the easiest is to measure the equivalent resistance during a typical transition. One of our main techniques to improve the delay is through transistor sizing, which we discussed in two fashions:» Setting the optimal ratio between the PUN/PDN.» Upsizing the gate to deal with a large output load. 66
67 An Intuitive Explanation 4. Static Operation 4.3 Dynamic Operation 4.4 Power Consumption 4.5 Summary And now that we fully understand the static and dynamic operation of the CMOS Inverter, it s time to take a look at POWER CONSUMPTION 67
68 Dynamic Power Assuming an ideal step input, we can analyze the energy consumed from the supply of the equivalent circuit during a LowtoHigh transition is given by: dv E i t V dt V C dt C V dv C V dt VDD out VDD 0 VDD DD DD 0 load load DD 0 out load DD Now, looking at the energy stored in the load capacitance, we get: dv C V E i t V dt C V dt C V dv VDD out load DD Charge 0 VDD out 0 load out load 0 out out dt 68
69 Dynamic Power E C V V load DD DD E Charge C load V DD Analyzing these results, we see that the energy required to charge the output capacitance is twice the energy stored on the capacitor at the end of the transition. This is relatively surprising and very important. It means that half of the energy was wasted on the pmos resistance independent of its size! 69
70 Dynamic Power Assuming the input changes now from zero to one, we now get a HightoLow transition. Here, the supply is disconnected, and the charge stored on the capacitance flows through the nmos to the ground. The energy dissipated is the total energy stored on the output capacitance, as no charge is left: dv C V E i t V dt C V dt C V dv 0 out load DD discharge 0 DSn out 0 load out load V out out dt DD The sum of the charge and discharge energy is obviously equal to the energy supplied: E E E C V charge discharge V load DD DD 70
71 Dynamic Power Conclusions:» Each charge and discharge cycle dissipates a fixed amount of energy, independent of the size of the device.» The effective energy is the charge stored on the capacitance. The rest of the energy is wasted as heat burned on the pmos (charge) and nmos (discharge) resistance. To compute the Power Dissipation, we calculate the total energy wasted per one second. For a circuit that completes a LowtoHigh transition f 01 times per second (and therefore a HightoLow transition as well ), the dynamic power consumption is: Pdyn CloadV DD f0 1 71
72 Dynamic Power We said that the Power Dissipation is a factor of the switching frequency of the gate. But the gate only switches when its input changes. In other words, the switching activity is smaller than the circuit frequency. We can rewrite the Dynamic Power expression using the activity factor, α of the inverter, expressing the probability of the output to switch: P C V f C V f dyn load DD eff DD C eff is the effective capacitance of a complex circuit, describing the average capacitance that actually switches each cycle. 7
73 Short Circuit Power During the above analysis, the input was an ideal step function, immediately closing one transistor when the other was opened. In a real circuit, the input signal has a nonzero rise/fall time, resulting in a time interval with both the pmos and nmos transistors open. This provides a direct path from V DD to GND, with a current known as Short Circuit current. This is shown in the following waveforms: 73
74 Short Circuit Power The energy dissipated via short circuit power is the area under the triangles: I peaktsc I peaktsc E V V t V I sc DD DD sc DD peak And the average power consumption is: Psc tscvdd I peak f 74
75 Short Circuit Power The short circuit interval, t sc, is the margin between the threshold voltages of the transistors. Assuming a linear input transition: t sc V DD V V DD T t rise( fall)
76 Short Circuit Power What affects the short circuit power?» A short input rise time with a large output capacitance (large fall time) minimizes short circuit power, as the peak current is very small. 76
77 Short Circuit Power What affects the short circuit power?» small output capacitance relative to the input rise time causes extensive short circuit power, as the peak current is maximal (saturation current of the transistors). Conclusion:» Try to keep the input and output rise/fall times similar to maximize performance and minimize short circuit power. 77
78 Static Power Ideally, a MOSFET transistor is a perfect switch. In such a case, a CMOS inverter never has a conducting path in steady state, resulting in no static power dissipation. However, in reality, MOSFET transistors never completely turn off. 78
79 Static Power Since static power is constantly consumed, the power dissipation can be simply expressed as: Pstatic IstaticVDD Sources of static power are beyond the scope of this course, however they are quickly becoming the dominant source of power in advanced submicron technologies. For further probing, see these subjects:» Subthreshold current» Hot Electrons» DIBL» Punchthrough 79
80 Total Power Consumption As we saw above, there are three components to the power dissipation of a CMOS inverter:» Dynamic Power» Short Circuit Power» Static Power Putting them all together, we get the total power consumption of a CMOS logic gate: P P P P fc V fv I t V I total dyn sc static load DD DD peak sc DD static 80
81 Total Power Consumption We previously learned that the powerdelayproduct (PDP) measures the average energy of a switching event: 1 PDP P t C V f t C V dyn pd load DD max pd load DD Since both Power and PDP give a clear advantage to energy reduction versus performance, we measure the energydelayproduct (EDP) as a combined measurement of the two: 1 EDP PDP t C V t pd load DD pd 81
82 An Intuitive Explanation 4. Static Operation 4.3 Dynamic Operation 4.4 Power Consumption 4.5 Summary Okay, enough with the inverter. But before we go on, let s go over a short SUMMARY 8
83 Summary The CMOS inverter is characterized by:» A pmos PullUp device and an nmos pull down device.» The pmos is usually wider due to inferior current driving.» An almost ideal VTC with a full rail to rail swing.» Noise margins of a balanced inverter are close to V DD /» The steady state response is not affected by fanout. Propagation delay:» Can be approximated as:» Small loads make faster drivers.» Widening the transistors improves the delay. Power Dissipation:» Dominated by dynamic power, given by: Reqp Reqn 0.69Cload» Short circuit power can be reduced by equating input/output slopes.» Static Power is a problem out of the scope of this course. t pd Pdyn fcloadv DD 83
The CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V
More informationDC and Transient Responses (i.e. delay) (some comments on power too!)
DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02  CMOS Transistor Theory & the Effects of Scaling
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More information5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1
5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design
More informationEEE 421 VLSI Circuits
EEE 421 CMOS Properties Full railtorail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady
More informationChapter 5. The Inverter. V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov Inverter
Chapter 5 The Inverter V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov.12 03 Objective of This Chapter Use Inverter to know basic CMOS Circuits Operations Watch for performance Index such as Speed (Delay calculation)
More informationECE 342 Solid State Devices & Circuits 4. CMOS
ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor NChannel MOSFET Built on ptype
More informationEE5311 Digital IC Design
EE5311 Digital IC Design Module 3  The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 6, 2017 Janakiraman, IITM
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More informationDigital Integrated Circuits
Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Shortcircuit current The CMOS inverter :
More informationCHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS
CHAPTER 5 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 5. CMOS Logic Gate Circuits 5. Digital Logic Inverters 5.3 The CMOS Inverter 5.4 Dynamic Operation of the CMOS Inverter 5.5 Transistor Sizing 5.6 Power
More informationLecture 6: DC & Transient Response
Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins
More informationEE5780 Advanced VLSI CAD
EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay
More informationCOMP 103. Lecture 10. Inverter Dynamics: The Quest for Performance. Section 5.4.2, What is this lecture+ about? PERFORMANCE
COMP 103 Lecture 10 Inverter Dynamics: The Quest for Performance Section 5.4.2, 5.4.3 [All lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated
More informationENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)
ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]
More informationMOSFET and CMOS Gate. Copy Right by Wentai Liu
MOSFET and CMOS Gate CMOS Inverter DC Analysis  Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models MOS
More informationLecture 12 Circuits numériques (II)
Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More informationLecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded
More informationDC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.
DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575604 yrpeng@uark.edu Pass Transistors We have assumed source is
More informationLecture 4: DC & Transient Response
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide
More informationEEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 8 Lecture #5: CMOS Inverter AC Characteristics Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Acknowledgments Slides due to Rajit Manohar from ECE 547 Advanced
More informationDC & Transient Responses
ECEN454 Digital Integrated Circuit Design DC & Transient Responses ECEN 454 DC Response DC Response: vs. for a gate Ex: Inverter When = > = When = > = In between, depends on transistor size and current
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NORgate C = NOT (A or B)
1 Introduction to TransistorLevel Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationEE5311 Digital IC Design
EE5311 Digital IC Design Module 3  The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 3, 2018 Janakiraman, IITM
More informationLecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:308:00pm in 105 Northgate
EE4Fall 2008 Digital Integrated Circuits Lecture VTCs and Delay Lecture # Announcements No lab today, Mon., Tues. Labs restart next week Midterm # Tues. Oct. 7 th, 6:308:00pm in 05 Northgate Exam is
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD V in V out C L CMOS Properties Full railtorail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler
More informationMidterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!
More informationCMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 14 The CMOS Inverter: dynamic behavior (sizing, inverter
More informationDigital Microelectronic Circuits ( )
Digital Microelectronic ircuits (36113021 ) Presented by: Dr. Alex Fish Lecture 5: Parasitic apacitance and Driving a Load 1 Motivation Thus far, we have learned how to model our essential building block,
More informationVLSI Design and Simulation
VLSI Design and Simulation CMOS Inverters Topics Inverter VTC Noise Margin Static Load Inverters CMOS Inverter FirstOrder DC Analysis R p V OL = 0 V OH = R n =0 = CMOS Inverter: Transient Response R p
More informationLecture 4: CMOS review & Dynamic Logic
Lecture 4: CMOS review & Dynamic Logic Reading: ch5, ch6 Overview CMOS basics Power and energy in CMOS Dynamic logic 1 CMOS Properties Full railtorail swing high noise margins Logic levels not dependent
More informationLecture 14  Digital Circuits (III) CMOS. April 1, 2003
6.12  Microelectronic Devices and Circuits  Spring 23 Lecture 141 Lecture 14  Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:
More informationEEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More information9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design
More informationECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model
ECE 34 Electronic Circuits Lecture 35 CMOS Delay Model Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More informationThe Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two
More informationMiscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]
Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an NSwitch, the
More informationECE321 Electronics I
ECE31 Electronics Lecture 1: CMOS nverter: Noise Margin & Delay Model Payman ZarkeshHa Office: ECE Bldg. 30B Office hours: Tuesday :003:00PM or by appointment Email: payman@ece.unm.edu Slide: 1 CMOS
More informationHightoLow Propagation Delay t PHL
HightoLow Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (nchannel) immediately switches from cutoff to saturation; the pchannel pullup switches from triode to
More informationLecture 13  Digital Circuits (II) MOS Inverter Circuits. March 20, 2003
6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 131 Lecture 13 Digital Circuits (II) MOS Inverter Circuits March 20, 2003 Contents: 1. NMOS inverter with resistor pullup (cont.) 2. NMOS
More informationAnnouncements. EE141 Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power
 Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 123pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances
More informationDigital Microelectronic Circuits ( ) Ratioed Logic. Lecture 8: Presented by: Mr. Adam Teman
Digital Microelectronic ircuits (36113021 ) Presented by: Mr. Adam Teman Lecture 8: atioed Logic 1 Motivation In the previous lecture, we learned about Standard MOS Digital Logic design. MOS is unquestionably
More informationEEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationDynamic operation 20
Dynamic operation 20 A simple model for the propagation delay Symmetric inverter (rise and fall delays are identical) otal capacitance is linear t p Minimum length devices R W C L t = 0.69R C = p W L 0.69
More informationEECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 111:3 Thursday, October 6, 6:38:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
More informationDigital Integrated Circuits 2nd Inverter
Digital Integrated Circuits The Inverter The CMOS Inverter V DD Analysis Inverter complex gate Cost V in V out complexity & Area Integrity and robustness C L Static behavior Performance Dynamic response
More information4.10 The CMOS Digital Logic Inverter
11/11/2004 section 4_10 The CMOS Digital Inverter blank.doc 1/1 4.10 The CMOS Digital Logic Inverter Reading Assignment: pp. 336346 Complementary MOSFET (CMOS) is the predominant technology for constructing
More informationCPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville
CPE/EE 47, CPE 57 VLSI Design I Delay Estimation Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: CMOS Circuit
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational
More informationDigital Integrated Circuits A Design Perspective
igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational
More information2007 Fall: Electronic Circuits 2 CHAPTER 10. DeogKyoon Jeong School of Electrical Engineering
007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits DeogKyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we
More information5. CMOS Gate Characteristics CS755
5. CMOS Gate Characteristics Last module: CMOS Transistor theory This module: DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Transistor ehavior 1) If the width of a transistor
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br
More informationWhere Does Power Go in CMOS?
Power Dissipation Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking
More informationPower Dissipation. Where Does Power Go in CMOS?
Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit
More informationEE115C Digital Electronic Circuits Homework #3
Electrical Engineering Department Spring 1 EE115C Digital Electronic Circuits Homework #3 Due Thursday, April, 6pm @ 56147E EIV Solution Problem 1 VTC and Inverter Analysis Figure 1a shows a standard
More informationCOMP 103. Lecture 16. Dynamic Logic
COMP 03 Lecture 6 Dynamic Logic Reading: 6.3, 6.4 [ll lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP03
More informationToday s lecture. EE141 Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
 Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
More informationCPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look
CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates epartment of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka )
More informationSpiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp
27.1 Spiral 2 7 Capacitance, Delay and Sizing Mark Redekopp 27.2 Learning Outcomes I understand the sources of capacitance in CMOS circuits I understand how delay scales with resistance, capacitance
More informationProperties of CMOS Gates Snapshot
MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)
More informationCMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties.
CMOS Inverter: Steady State Response CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates R p V OL = V OH = V M = f(r n, R p ) epartment of Electrical and Computer Engineering University
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationTopic 4. The CMOS Inverter
Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ Email: p.cheung@ic.ac.uk Topic 41 Noise in Digital Integrated
More informationB.Supmonchai July 5th, q Quantification of Design Metrics of an inverter. q Optimization of an inverter design. B.Supmonchai Why CMOS Inverter?
July 5th, 4 Goals of This Chapter Quantification of Design Metrics of an inverter Static (or SteadyState) Behavior Chapter 5 CMOS Inverter Boonchuay Supmonchai Integrated Design Application Research (IDAR)
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 10: February 15, 2018 MOS Inverter: Dynamic Characteristics Penn ESE 570 Spring 2018 Khanna Lecture Outline! Inverter Power! Dynamic Characteristics
More informationEE 434 Lecture 33. Logic Design
EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The twoinverter loop X Y X
More informationEECS 427 Lecture 11: Power and Energy Reading: EECS 427 F09 Lecture Reminders
EECS 47 Lecture 11: Power and Energy Reading: 5.55 [Adapted from Irwin and Narayanan] 1 Reminders CAD5 is due Wednesday 10/8 You can submit it by Thursday 10/9 at noon Lecture on 11/ will be taught by
More informationEE115C Winter 2017 Digital Electronic Circuits. Lecture 6: Power Consumption
EE115C Winter 2017 Digital Electronic Circuits Lecture 6: Power Consumption Four Key Design Metrics for Digital ICs Cost of ICs Reliability Speed Power EE115C Winter 2017 2 Power and Energy Challenges
More informationEE115C Digital Electronic Circuits Homework #4
EE115 Digital Electronic ircuits Homework #4 Problem 1 Power Dissipation Solution Vdd =1.0V onsider the source follower circuit used to drive a load L =20fF shown above. M1 and M2 are both NMOS transistors
More informationCMOS Technology for Computer Architects
CMOS Technology for Computer Architects Recap Technology Trends Lecture 2: Transistor Inverter Iakovos Mavroidis Giorgos Passas Manolis Katevenis FORTHICS (University of Crete) 1 2 Recap Threshold Voltage
More informationCMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic [dapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey,. Chandrakasan,. Nikolic] Sp11 CMPEN 411
More informationThe Inverter. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Inverter Revised from Digital Integrated Circuits, Jan M. Rabaey el, 2003 Propagation Delay CMOS
More informationENEE 359a Digital VLSI Design
SLIDE 1 ENEE 359a Digital VLSI Design & Logical Effort Prof. blj@ece.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay
More informationCheck course home page periodically for announcements. Homework 2 is due TODAY by 5pm In 240 Cory
EE141 Fall 005 Lecture 6 MOS Capacitances, Propagation elay Important! Check course home page periodically for announcements Homework is due TOAY by 5pm In 40 Cory Homework 3 will be posted TOAY ue Thursday
More informationPractice 7: CMOS Capacitance
Practice 7: CMOS Capacitance Digital Electronic Circuits Semester A 2012 MOSFET Capacitances MOSFET Capacitance Components 3 Gate to Channel Capacitance In general, the gate capacitance is similar to a
More informationUsing MOS Models. C.K. Ken Yang UCLA Courtesy of MAH EE 215B
Using MOS Models C.K. Ken Yang UCLA yangck@ucla.edu Courtesy of MAH 1 Overview Reading Rabaey 5.4 W&H 4.2 Background In the past two lectures we have reviewed the iv and CV curves for MOS devices, both
More informationObjective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components
Objective: Power Components Outline: 1) Acknowledgements 2) Objective and Outline 1 Acknowledgement This lecture note has been obtained from similar courses all over the world. I wish to thank all the
More informationLecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
More informationInterconnect (2) Buffering Techniques. Logical Effort
Interconnect (2) Buffering Techniques. Logical Effort Lecture 14 18322 Fall 2002 Textbook: [Sections 4.2.1, 8.2.3] A few announcements! M1 is almost over: The checkoff is due today (by 9:30PM) Students
More informationEE213, Spr 2017 HW#3 Due: May 17 th, in class. Figure 1
RULES: Please try to work on your own. Discussion is permissible, but identical submissions are unacceptable! Please show all intermediate steps: a correct solution without an explanation will get zero
More informationReview of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model
Content MOS Devices and Switching Circuits Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model A Cantoni 20092013 Digital Switching 1 Content MOS
More informationLecture 12 CMOS Delay & Transient Response
EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 12 CMOS Delay & Transient Response Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology
More informationEEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #3: CMOS Inverters MOS Scaling Rajeevan Amirtharajah University of California, Davis Jeff Parhurst Intel Corporation Outline Review: Inverter Transfer Characteristics Lecture 3: Noise Margins,
More informationImportant! EE141 Fall 2002 Lecture 5. CMOS Inverter MOS Transistor Model
 Fall 00 Lecture 5 CMO Inverter MO Transistor Model Important! Lab 3 this week You must show up in one of the lab sessions this week If you don t show up you will be dropped from the class» Unless you
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown.
More informationElectronic Devices and Circuits Lecture 16  Digital Circuits: CMOS  Outline Announcements (= I ON V DD
6.01  Electronic Deices and Circuits Lecture 16  Digital Circuits: CMOS  Outline Announcements Handout; Web posting  Lecture Outline and Summary; two readings Exam  Wednesday, No. 5, 7:309:30 pm,
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 10: February 16, 2016 MOS Inverter: Dynamic Characteristics Lecture Outline! Review: Symmetric CMOS Inverter Design! Inverter Power! Dynamic
More informationPractice 3: Semiconductors
Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given
More information