# 5. CMOS Gate Characteristics CS755

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1 5. CMOS Gate Characteristics Last module: CMOS Transistor theory This module: DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Transistor ehavior 1) If the width of a transistor increases, the current will ) If the length of a transistor increases, the current will ) If the supply voltage of a chip increases, the maimum transistor current will 4) If the width of a transistor increases, its gate capacitance will 5) If the length of a transistor increases, its gate capacitance will 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 1 CS755 Karu Sankaralingam 5. CMOS Gate Characteristics DC Response Transistor Operation DC Response: vs. for a gate E: Inverter When = -> = When = -> = V In between, depends on DD transistor size and current I V dsp in y KCL, must settle such that = I dsp We could solve equations ut graphical solution gives more insight Current depends on region of transistor behavior For what and are nmos and pmos in Cutoff? Linear? Saturation? CS755 Karu Sankaralingam 5. CMOS Gate Characteristics CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 4 1

2 nmos Operation pmos Operation Cutoff Linear Saturated Cutoff Linear Saturated V gsn < V tn V gsn > V tn V gsn > V V gsp > V tp V gsp < V tp V gsp < V tp tn < V tn > V tn > V > + V tp < + V tp < + V tp tn V dsn < V gsn V tn V dsn > V gsn V V dsp > V gsp V tp V dsp < V gsp V tp tn < - V tn > - V > - V tp < - V tp tn V gsn = V dsn = I dsp V gsp = - V dsp = - V tp < I dsp CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 5 CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 6 I-V Characteristics Current vs., Make pmos wider than nmos such that b n = b p V gsn5 5 V gsn4 -V gsp1 V gsp -V dsp V gsn V gsn V gsn1, I dsp V gsp V dsn V gsp4 -I dsp V gsp5 CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 7 CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 8

3 For a given : Plot, I dsp vs. must be where currents are equal in = 5, I dsp, I dsp I dsp CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 9 CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 1 =. =.4 Idsn, I dsp, I dsp CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 11 CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 1

4 =.6 =.8, I dsp, I dsp CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 1 CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 14 Load Line Summary = 5 5, I dsp, I dsp CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 15 CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 16 4

5 DC Transfer Curve Operating Regions Transcribe points onto vs. plot Revisit transistor operating regions 5 C D E V tn / +V tp Region nmos pmos Cutoff Linear Saturation Linear C Saturation Saturation D Linear Saturation E Linear Cutoff C D E V tn / +V tp CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 17 CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 18 eta Ratio If b p / b n 1, switching point will move from / Called skewed gate Other gates: collapse into equivalent inverter b p bn.1 CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 19 b p bn Noise Margins How much noise can a gate input see before it does not recognize the input? Logical High Output Range Logical Low Output Range Output Characteristics Input Characteristics V OH NM H V IH V OL NM L GND V IL Indeterminate Region Logical High Input Range Logical Low Input Range CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 5

6 Logic Levels Transient Response To maimize noise margins, select logic levels at unity gain point of DC transfer characteristic V OH Unity Gain Points Slope = -1 b p /b n > 1 DC analysis tells us if is constant Transient analysis tells us (t) if (t) changes Requires solving differential equations Input is usually considered to be a step or ramp From to or vice versa V OL V tn V IL V V IH DD - V tp CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 1 CS755 Karu Sankaralingam 5. CMOS Gate Characteristics Inverter Step Response E: find step response of inverter driving load cap V () t u( t t ) V I dsn V in out ( t t ) V DD DD dvo ut ( t) Id sn () t dt C load t t t) V V V V b ( t) b VDD V t V out () t VD D Vt ( DD DD t (t) (t) CS755 Karu Sankaralingam 5. CMOS Gate Characteristics t (t) (t) (t) C load t Delay Definitions t pdr : rising propagation delay Ma time from input to rising output crossing / t pdf : falling propagation delay Ma time from input to falling output crossing / t pd : average propagation delay t pd = (t pdr + t pdf )/ t r : rise time From output crossing. to.8 t f : fall time From output crossing.8 to. CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 4 6

7 Delay Definitions Simulated Inverter Delay t cdr : rising contamination delay Minimum time from input to rising output crossing / t cdf : falling contamination delay Minimum time from input to falling output crossing / t cd : average contamination delay t pd = (t cdr + t cdf )/ Solving differential equations by hand too hard SPICE simulator solves equations numerically Uses more accurate I-V models too! ut simulations take time to write (V) t pdf = 66ps t pdr = 8ps.. p 4p 6p 8p 1n t(s) CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 5 CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 6 Delay Estimation We would like to be able to easily estimate delay Not as accurate as simulation ut easier to ask What if? The step response usually looks like a 1 st order RC response with a decaying eponential. Use RC delay models to estimate delay C = total capacitance on output node Use effective resistance R So that t pd = RC Characterize transistors by finding effective R Depends on average current as gate switches CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 7 RC Delay Models Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nmos has resistance R, capacitance C Unit pmos has resistance R, capacitance C Capacitance proportional to width Resistance inversely proportional to width d g k s R/k g d s CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 8 g d k s g s R/k d 7

8 Eample: -input NND -input NND Caps Sketch a -input NND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). nnotate the -input NND gate with gate and diffusion capacitance. CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 9 CS755 Karu Sankaralingam 5. CMOS Gate Characteristics Elmore Delay ON transistors look like resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder t R C pd itosource i nodes i R C R R C R R R C N N Eample: -input NND Estimate worst-case rising and falling delay of -input NND driving h identical gates. R 1 R R R N C 1 C C C N CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 1 CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 8

9 Eample: -input NND Eample: -input NND Estimate rising and falling propagation delays of a -input NND driving h identical gates. Estimate rising and falling propagation delays of a -input NND driving h identical gates. 6C C 4hC 6C C 4hC R (6+4h)C tpdr CS755 Karu Sankaralingam 5. CMOS Gate Characteristics CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 4 Eample: -input NND Estimate rising and falling propagation delays of a -input NND driving h identical gates. Eample: -input NND Estimate rising and falling propagation delays of a -input NND driving h identical gates. 6C C 4hC 6C 4hC C R t 64 (6+4h)C pdr h RC CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 5 CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 6 9

10 Eample: -input NND Delay Components Estimate rising and falling propagation delays of a -input NND driving h identical gates. R/ R/ C (6+4h)C 6C C pdf 4hC R R R h RC t C h C Delay has two parts Parasitic delay 6 or 7 RC Independent of load Effort delay 4h RC Proportional to load capacitance CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 7 CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 8 Contamination Delay est-case (contamination) delay can be substantially less than propagation delay. E: If both inputs fall simultaneously R R (6+4h)C 6C tcdr C 4hC CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 9 h RC Diffusion Capacitance ssumed contacted diffusion on every s/d Good layout minimizes diffusion area E: NND layout shares one diffusion contact Reduces output capacitance by C Merged uncontacted diffusion might help too Shared Contacted Diffusion Merged Uncontacted Diffusion C C C C C Isolated Contacted Diffusion CS755 Karu Sankaralingam 5. CMOS Gate Characteristics 4 7C C C Note. This picture from tetbook assumes that uncontacted diffusion had the same unit capacitance C. ctually, it can be less, e.g., C/. 1

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