Lecture 5: DC & Transient Response


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1 Lecture 5: DC & Transient Response
2 Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2
3 Activity 1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change DC Response CMOS VLSI Design Slide 3
4 Activity 1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change DC Response CMOS VLSI Design Slide 4
5 Pass Transistors q We have assumed source is grounded q What if source > 0? e.g. pass transistor passing q V g = If V s > V t, V gs < V t Hence transistor would turn itself off q nmos pass transistors pull no higher than V tn Called a degraded 1 Approaches degraded value slowly (low I ds ) q pmos pass transistors pull no lower than V tp q Transmission gates are needed to pass both 0 and 1 5
6 Pass Transistor Ckts V s = V tn V tn V tn V tn V s = V tp V tn 2V tn V SS 6
7 DC Response q DC Response: V out vs. V in for a gate q Example: Inverter When V in = 0 > V out = When V in = > V out = 0 In between, V out depends on transistor size and current By KCL, must settle such that I dsn = I dsp We could solve equations V in But graphical solution gives more insight I dsp I dsn V out 7
8 Transistor Operation q Current depends on region of transistor behavior q For what V in and V out are nmos and pmos in Cutoff? Linear? Saturation? 8
9 nmos Operation Cutoff Linear Saturated V gsn < V tn V in < V tn V gsn > V tn V in > V tn V dsn < V gsn V tn V out < V in  V tn V gsn > V tn V in > V tn V dsn > V gsn V tn V out > V in  V tn V gsn = V in I dsp V dsn = V out V in I dsn V out 9
10 pmos Operation Cutoff Linear Saturated V gsp > V tp V in > + V tp V gsp < V tp V in < + V tp V dsp > V gsp V tp V out > V in  V tp V gsp < V tp V in < + V tp V dsp < V gsp V tp V out < V in  V tp V gsp = V in  V tp < 0 V dsp = V out  V in I dsp I dsn V out 10
11 IV Characteristics q Make pmos wider than nmos such that β n = β p V gsn5 I dsn V gsn4 V dsp V gsn3 V gsp1 V gsp20 V gsn2 V gsn1 V gsp3 V dsn V gsp4 I dsp V gsp5 11
12 Current vs. V out, V in V in0 V in5 I dsn, I dsp V in1 V in4 V in2 V in3 V in3 V in4 V in2 V in1 V out 12
13 Load Line Analysis q For a given V in : Plot I dsn, I dsp vs. V out V out must be where currents are equal V in0 V in5 I dsn, I dsp V in1 V in4 V in2 V in3 V in3 V in4 V in2 V in1 V in I dsn V out I dsp V out 13
14 Load Line Analysis q V in = 0.2V0 0.4V 0.6V 0.8V DD V in0 V in5 I dsn, I dsp V in1 V in4 V in2 V in3 V in3 V in4 V in2 V in0 in1 V out out DD 14
15 DC Transfer Curve q Transcribe points onto V in vs. V out plot V in0 V in5 A B V in0 V in1 V in2 V in1 V in4 V out C V in2 V in3 V in3 V in4 V in2 V in1 0 V in3 D V in4 V E in5 V tn /2 +V tp V out V in 15
16 Operating Regions q Revisit transistor operating regions V in V out Region nmos pmos A Cutoff Linear B Saturation Linear C Saturation Saturation D Linear Saturation E Linear Cutoff V out A B 0 C D E V tn /2 +V tp V in 16
17 Beta Ratio q If β p / β n 1, switching point will move from /2 q Called skewed gate V out β p 0.1 β = n β p 10 β = n V in 17
18 Noise Margins q How much noise can a gate input see before it does not recognize the input? Logical High Output Range Output Characteristics V OH NM H Input Characteristics Logical High Input Range V IH V IL Indeterminate Region Logical Low Output Range V OL NM L GND Logical Low Input Range 18
19 Logic Levels q To maximize noise margins, select logic levels at unity gain point of DC transfer characteristic V out Unity Gain Points Slope = 1 V OH β p /β n > 1 V in V out V OL 0 V tn V IL V IH  V tp V in 19
20 Transient Response q DC analysis tells us V out if V in is constant q Transient analysis tells us V out (t) if V in (t) changes Requires solving differential equations q Input is usually considered to be a step or ramp From 0 to or vice versa 20
21 Inverter Step Response I q Ex: find step response of inverter driving load cap dsn V V in out dv () t = ut ( ( t < t ) out dt ( t) 0 = t) V 0 = V I DD dsn C DD () t load 0 t t0 β 2 ( t) = 2 ( VDD Vt ) Vout > VDD Vt Vout () t β VDD V t V () 2 out t Vo ut < VD D Vt V in (t) t 0 I dsn (t) V in (t) V out (t) V out (t) C load t 21
22 Delay Definitions q q q q q t pdr : rising propagation delay From input to rising output crossing /2 t pdf : falling propagation delay From input to falling output crossing /2 t pd : average propagation delay t pd = (t pdr + t pdf )/2 t r : rise time From output crossing 0.2 to 0.8 t f : fall time From output crossing 0.8 to
23 Delay Definitions q t cdr : rising contamination delay From input to rising output crossing /2 q t cdf : falling contamination delay From input to falling output crossing /2 q t cd : average contamination delay t pd = (t cdr + t cdf )/2 23
24 Simulated Inverter Delay q Solving differential equations by hand is too hard q SPICE simulator solves the equations numerically Uses more accurate IV models too! q But simulations take time to write, may hide insight (V) V in t pdf = 66ps t pdr = 83ps 0.5 V out p 400p 600p 800p 1n t(s) 24
25 Delay Estimation q We would like to be able to easily estimate delay Not as accurate as simulation But easier to ask What if? q The step response usually looks like a 1 st order RC response with a decaying exponential. q Use RC delay models to estimate delay C = total capacitance on output node Use effective resistance R So that t pd = RC q Characterize transistors by finding their effective R Depends on average current as gate switches 25
26 Effective Resistance q Shockley models have limited value Not accurate enough for modern transistors Too complicated for much hand analysis q Simplification: treat transistor as resistor Replace I ds (V ds, V gs ) with effective resistance R I ds = V ds /R R averaged across switching of digital gate q Too inaccurate to predict current at any given time But good enough to predict RC delay 26
27 RC Delay Model q Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nmos has resistance R, capacitance C Unit pmos has resistance 2R, capacitance C q Capacitance proportional to width q Resistance inversely proportional to width g d k s g R/k kc d s kc kc 27 g d k s g kc s d 2R/k kc kc
28 RC Values q Capacitance C = C g = C s = C d = 2 ff/µm of gate width in 0.6 µm Gradually decline to 1 ff/µm in 65 nm q Resistance R 10 KΩ µm in 0.6 µm process Improves with shorter channel lengths 1.25 KΩ µm in 65 nm process q Unit transistors May refer to minimum contacted device (4/2 λ) Or maybe 1 µm wide device Doesn t matter as long as you are consistent 28
29 Inverter Delay Estimate q Estimate the delay of a fanoutof1 inverter R 2C A 2 1 Y 2 1 R 2C C Y 2C C R 2C C 2C C C d = 6RC 29
30 Delay Model Comparison 30
31 Example: 3input NAND q Sketch a 3input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R)
32 3input NAND Caps q Annotate the 3input NAND gate with gate and diffusion capacitance. 2C 2C 2C 2C 2C C 2C 5C 5C 5C 3C 3C 3C C 2C 9C 3C 3C 3C 3C 32
33 Elmore Delay q ON transistors look like resistors q Pullup or pulldown network modeled as RC ladder q Elmore delay of RC ladder t R C pd i to source i nodes i = RC + R + R C R + R R C ( ) ( ) R 1 R 2 R 3 R N N N C 1 C 2 C 3 C N 33
34 Example: 3input NAND q Estimate worstcase rising and falling delay of 3input NAND driving h identical gates h copies 3 3 n 1 9C n 2 3C 3C Y 5hC tpdr ( 9 5 ) = + h RC pdf ( 3 R R R R R R )( ) ( 3 3 )( 3 3) ( 9 5 ) ( 3 3 3) ( 12 5h) RC t = C + C h C + + = + 34
35 Delay Components q Delay has two parts Parasitic delay 9 or 12 RC Independent of load Effort delay 5h RC Proportional to load capacitance 35
36 Contamination Delay q q Bestcase (contamination) delay can be substantially less than propagation delay. Ex: If all three inputs fall simultaneously n 1 9C n 2 3C 3C Y 5hC R 5 tcdr = ( 9+ 5h) C = 3+ h RC
37 Diffusion Capacitance q We assumed contacted diffusion on every s / d. q Good layout minimizes diffusion area q Ex: NAND3 layout shares one diffusion contact Reduces output capacitance by 2C Merged uncontacted diffusion might help too Shared Contacted Diffusion Merged Uncontacted Diffusion 2C 2C Isolated Contacted Diffusion C 3C 3C 3C 3C 3 3C 37
38 Layout Comparison q Which layout is better? A B A B Y Y GND GND 38
39 Summary q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 39
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