Lecture 5: DC & Transient Response


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1 Lecture 5: DC & Transient Response
2 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2
3 Pass Transistors We have assumed source is grounded What if source > 0? e.g. pass transistor passing V g = If V s > V t, V gs < V t Hence transistor would turn itself off nmos pass transistors pull no higher than V tn Called a degraded 1 Approach degraded value slowly (low I ds ) pmos pass transistors pull no lower than V tp Transmission gates are needed to pass both 0 and 1 3
4 Pass Transistor Ckts 4
5 DC Response DC Response: V out vs. V in for a gate Ex: Inverter When V in = 0 > V out = When V in = > V out = 0 In between, V out depends on transistor size and current By KCL, must settle such that V in I dsn = I dsp We could solve equations But graphical solution gives more insight I dsp I dsn V out 5
6 Transistor Operation Current depends on region of transistor behavior For what V in and V out are nmos and pmos in Cutoff? Linear? Saturation? 6
7 nmos Operation Cutoff V gsn < V tn V in < V tn Linear V gsn > V tn V in > V tn V dsn < V gsn V tn V out < V in V tn Saturated V gsn > V tn V in > V tn V dsn > V gsn V tn V out > V in V tn V gsn = V in I dsp V dsn = V out V in I dsn V out 7
8 pmos Operation Cutoff V gsp > V tp V in > + V tp Linear V gsp < V tp V in < + V tp V dsp > V gsp V tp V out > V in V tp Saturated V gsp < V tp V in < + V tp V dsp < V gsp V tp V out < V in V tp V gsp = V in  V tp < 0 V dsp = V out  V in I dsp I dsn V out 8
9 IV Characteristics Make pmos is wider than nmos such that β n = β p 9
10 Current vs. V out, V in V in0 V in5 I dsn, I dsp V in1 V in4 V in2 V in3 V in3 V in4 V in2 V in1 V out 10
11 Load Line Analysis For a given V in : Plot I dsn, I dsp vs. V out V out must be where currents are equal in V in0 V in5 I dsn, I dsp V in1 V in4 V in2 V in3 I dsp V in3 V in4 V in2 V in1 V in I dsn V out V out 11
12 Load Line Analysis V in = 0.2V 0.4V 0.6V 0.8V DD V in0 V in5 I dsn, I dsp dsn dsp V in1 V in4 V in2 V in3 V in3 V in4 V in2 V in0 in1 V out 12
13 DC Transfer Curve Transcribe points onto V in vs. V out plot V in0 V in5 A B V in0 V in1 V in2 V in1 V in4 V out C V in2 V in3 V in3 V in4 V in2 V in1 0 V in3 D V in4 V E in5 V tn /2 +V tp V out V in 13
14 Operating Regions Revisit transistor operating regions Region nmos pmos A B Cutoff Saturation Linear Linear A B C D Saturation Linear Saturation Saturation V out C E Linear Cutoff 0 D E V tn /2 +V tp V in 14
15 Beta Ratio If β p / β n 1, switching point will move from /2 Called skewed gate Other gates: collapse into equivalent inverter V out β p 0.1 β = n β p 10 β = n V in 15
16 Noise Margins How much noise can a gate input see before it does not recognize the input? Logical High Output Range Output Characteristics V OH NM H Input Characteristics Logical High Input Range V IH V IL Indeterminate Region Logical Low Output Range V OL NM L GND Logical Low Input Range 16
17 Logic Levels To maximize noise margins, select logic levels at unity gain point of DC transfer characteristic V out Unity Gain Points Slope = 1 V OH β p /β n > 1 V in V out V OL 0 V tn V IL V IH  V tp V in 17
18 Transient Response DC analysis tells us V out if V in is constant Transient analysis tells us V out (t) if V in (t) changes Requires solving differential equations Input is usually considered to be a step or ramp From 0 to or vice versa 18
19 Inverter Step Response I Ex: find step response of inverter driving load cap V V in out () t = ut ( ( t < t ) dvo ut ( t) dt 0 = t) V 0 = V I C 0 DD dsn DD () t load 0 β 2 dsn ( t) = 2 ( VDD V) Vout > VDD Vt Vout ( t) β VDD V t V () t V < V 2 D V out out D t t t V in (t) t 0 I dsn (t) V in (t) V out (t) V out (t) C load t 19
20 Delay Definitions t pdr : rising propagation delay From input to rising output crossing /2 t pdf : falling propagation delay From input to falling output crossing /2 t pd : average propagation delay t pd = (t pdr + t pdf )/2 t r : rise time From output crossing 0.2 to 0.8 t f : fall time From output crossing 0.8 to
21 Delay Definitions t cdr : rising contamination delay From input to rising output crossing /2 t cdf : falling contamination delay From input to falling output crossing /2 t cd : average contamination delay t pd = (t cdr + t cdf )/2 21
22 Simulated Inverter Delay Solving differential equations by hand is too hard SPICE simulator solves the equations numerically Uses more accurate IV models too! But simulations take time to write, may hide insight (V) V in t pdf = 66ps t pdr = 83ps 0.5 V out p 400p 600p 800p 1n t(s) 22
23 Delay Estimation We would like to be able to easily estimate delay Not as accurate as simulation But easier to ask What if? The step response usually looks like a 1 st order RC response with a decaying exponential. Use RC delay models to estimate delay C = total capacitance on output node Use effective resistance R So that t pd = RC Characterize transistors by finding their effective R Depends on average current as gate switches 23
24 Effective Resistance Shockley models have limited value Not accurate enough for modern transistors Too complicated for much hand analysis Simplification: treat transistor as resistor Replace I ds (V ds, V gs ) with effective resistance R I ds = V ds /R R averaged across switching of digital gate Too inaccurate to predict current at any given time But good enough to predict RC delay 24
25 RC Delay Model Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nmos has resistance R, capacitance C Unit pmos has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width d s kc kc R/k d 2R/k d g k g kc g k g s kc kc s kc s d 25
26 RC Values Capacitance C = C g = C s = C d = 2 ff/μm of gate width in 0.6 μm Gradually decline to 1 ff/μm in nanometer techs. Resistance R 6 KΩ*μm in 0.6 μm process Improves with shorter channel lengths Unit transistors May refer to minimum contacted device (4/2 λ) Or maybe 1 μm wide device Doesn t matter as long as you are consistent 26
27 Inverter Delay Estimate Estimate the delay of a fanoutof1 inverter R 2C A 2 1 Y 2 1 R 2C C Y 2C C R 2C C 2C C C d = 6RC 27
28 Delay Model Comparison 28
29 Example: 3input NAND Sketch a 3input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R)
30 3input NAND Caps Annotate the 3input NAND gate with gate and diffusion capacitance. 2C 2C 2C 2C 2C C 2C 2C 2C 3C 3C 3C C 3C 3C 3C 30
31 Elmore Delay ON transistors look like resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder t R C pd i to source i nodes i = R C + R + R C R + R R C ( ) ( ) R 1 R 2 R 3 R N N N C 1 C 2 C 3 C N 31
32 Example: 3input NAND Estimate worstcase rising and falling delay of 3input NAND driving h identical gates n 1 9C n 2 3C 3C Y 5hC tpdr ( 9 5 ) = + h RC pdf ( 3 R R R R R R )( ) ( 3 3 )( 3 3) ( 9 5 ) ( 3 3 3) ( 11 5h) RC t = C + C h C + + = + 32
33 Delay Components Delay has two parts Parasitic delay 9 or 11 RC Independent of load Effort delay 5h RC Proportional to load capacitance 33
34 Contamination Delay Bestcase (contamination) delay can be substantially less than propagation delay. Ex: If all three inputs fall simultaneously n 1 9C n 2 3C 3C Y 5hC R 5 tcdr = ( 9+ 5h) C = 3+ h RC
35 Diffusion Capacitance We assumed contacted diffusion on every s / d. Good layout minimizes diffusion area Ex: NAND3 layout shares one diffusion contact Reduces output capacitance by 2C Merged uncontacted diffusion might help too Shared Contacted Diffusion Merged Uncontacted Diffusion 2C 2C Isolated Contacted Diffusion C 3C 3C 3C 3C 3 3C 35
36 Layout Comparison Which layout is better? A B A B Y Y GND GND 36
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