The Physical Structure (NMOS)


 Gerald Haynes
 3 years ago
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1 The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1
2 Transistor Resistance Two Components: Drain/ Sources Resistance: R D(S) = Rsh x no. of squares+ contact resistance. : (G) (S) n+ n+ L W (D) Channel Resistance: Depends on the region of operation: 1 R CH ' = K' R 2 CH K' W  V L GS V T V DS W  V V L GS T R S Rch R D Linear = Saturation 2
3 Transistor Geometry 3
4 Transistor Geometry Detailed 4
5 NMOS OperationLinear I DS N K N 1 2 V GSN V TN V DSN V DSN 2 = K N =K. W/L K = C ox Process Transconductance ua/v 2 for 0.35u, K (Kp)=196uA/ V C ox 2 ox = Gate oxide capacitance per unit area t ox ox = 3.9 x o = 3.45 x F/m t ox Oxide thickness for 0.35, tox=100a o Quick calculation of Cox: Cox= 0.345/tox (A o ) pf/um 2 = mobility of electrons 550 cm 2 /Vsec for 0.35 process I DS VGS V DS 5
6 NMOS OperationLinear Effect of W/L W/L Rds W W Effect of temperature temp Rds 6
7 Variations in Width and Length 1. Width Oxide encroachment polysilicon W eff = W drawn 2W D W D W eff W drawn W D polysilicon 2. Length Lateral diffusion L D = 0.7Xj L eff = L drawn 2L D L drawn L D L eff L D 7
8 Large Transistors R channel decrease with increase of W/L of the transistor 8
9 Semiconductor Resistors R= p(l /A) = (p/t). (l /w) = Rsh. (l /w) For 0.5u process: N+ diffusion : 70 / M1: 0.06 P+ diffusion : 140 / M2: 0.06 Polysilicon : 12 / M3: 0.03 Polycide:23 / Pwell: 2.5K Nwell: 1K w (A) = n n q+ p p q l current Rsh values for 0.35u CMOS Process: Polysilicon 10 / Polycide 2 / Contact resistance: PolyI to MetalI 50 Metal / Via resistance: Metal I to Metal II 1.5 Metal II 0.07 / Via resistance: Metal II to metal III 1. Metal III 0.05 / t 9
10 Modelling: Resistance 1. Resistance: Rint= Rsh [l/w] Rsh values for 0.35u CMOS Process: Polysilicon 10 / Polycide 2 / Metal / Metal II 0.07 / Metal III 0.05 / Contact resistance: PolyI to MetalI 50 Via resistance: Metal I to Metal II 1.5 Via resistance: Metal II to metal III 1. 10
11 Semiconductor Resistors polysilicon Diffusion n+ Field oxide Al SiO2 n+ Al Polysilicon Resistor Diffusion Resistor 11
12 Delay Definitions V in 50% t phl t plh t V out 90% 50% t f 10% t r t 12
13 Semiconductor Capacitors 1. Poly Capacitor: a. Poly to substrate b. Poly1 to Poly2 2. Diffusion Capacitor sidewall capacitances depletion region n+ (N D ) substrate (N A ) bottomwall capacitance 13
14 Dynamic Behavior of MOS Transistor G C GS C GD S D C SB C GB C DB B 14 Prentice Hall/Rabaey
15 SPICE Parameters for Parasitics 15 Prentice Hall/Rabaey
16 SPICE Transistors Parameters 16 Prentice Hall/Rabaey
17 Computing the Capacitances V DD V DD V in C gd 12 M 2 C db 2 V out C g 4 M 4 V out 2 M 1 C db 1 C w Interconnect C g 3 M 3 Fanout Simplified Model V in V out C L 17
18 Computing the Capacitances 18
19 CMOS Inverter: Steady State Response V DD V DD R on V OH = V DD V out V out V OL = 0 R on V in = V DD V in = 0 19
20 Switching Characteristics of Inverters Transient Response V DD t phl = f(r on.c L ) = 0.69 R on C L V out V out ln(0.5) R on C L 1 V DD V in = V DD R on C L t 20
21 Step Response Fall Delay Time: TPHL MN OFF Saturation Linear G VDD=5V S I DN V in = 5 Vin VDD MP D Vo V in = 4 V in = 3 Vin G MN D S CL VDDVT (VDSAT) VDD Vo GND 21
22 Step Response Fall time, tf t f = C L K ( n 0.1) N VDD( 1 n) ln( ( 1 n) 19 20n ) vo n t f =~ k. C. V n L DD k is a constant vin 0.1 t r = C L K P VDD( 1 + p) ( )( p) + ln ( ( 1 + p) p ) td1 td2 t r =~ k. C. V p L DD k is a constant 22
23 Step ResponsetPHL Assume normalized voltages vin= Vin/ VDD vo= Vo/ VDD n = V TN / VDD p = V TP / VDD Vx Vo VDD/ 2 Vin VDD VDDVTN t PHL =td1+td2 td1 td2 t PHL t PHL = = C L K N VDD( 1 n) C L A' N K N VDD 2n ( ln( 1 n) 3 4n ) vo 0.5 vin td1 1 1n td2 23
24 Step Response Rise Delay t PLH and Rise Time t r VDD t PLH = C L K P VDD ( 1 + p ) 2p ( ln( 1 + p) 3 + 4p ) G S t PLH = C L A' P K P VDD Vin VDD MP D Vo t r = C L K P VDD( 1 + p) ( ) 0.1 ( 1 + p) + ln ( ( 1 + p) p ) G MN D S CL t r 4C L A' P K P VDD = (P=  0.2) GND 24
25 Factors Influence Delay Inverter Delay,td = (t PHL +t PLH )/2 The following factors influence the delay of the inverter: Load Capacitance Supply Voltage Transistor Sizes Junction Temperature Input Transition Time 25
26 Delay as a function of V DD Normalized Delay V DD (V) 26
27 Delay as a function of Transistor Size t PHL and t f decrease with the increase of W/L of the NMOS t PLH and t r decrease with the increase of W/L of the PMOS 27
28 Temperature Effect Temperature ranges: commercial : 0 to70 0 C industrial: 40 to 85 0 C military: 55 to C Calculation of the junction temperature t j = t a + ja X Pd Effect of temperature on mobility Delay and speed implications 28
29 Effect of Input Transition Times The delay of the inverter increases with the increase of the input transition times r and f Vin r Vo t PHL = (t PHL ) step + ( r /6).(12p) t PLH = (t PLH ) step + ( f /6).(1+2n) 29
30 Transistor Sizing Define = (W/L)p/(W/L)n For Equal Fall and Rise Delay K N =K P = n / p For Minimum Delay dt D /d = 0 opt = Sqrt ( n / p ) 30
31 Power Dissipation in CMOS Two Components contribute to the power dissipation:» Static Power Dissipation Leakage current Subthreshold current» Dynamic Power Dissipation Short circuit power dissipation Charging and discharging power dissipation 31
32 Static Power Dissipation Leakage Current: PN junction reverse biased current: i o = i s (e qv/kt 1) Typical value 0.1nA to temp. Vin Total Power dissipation: P sl = i 0.V DD Subthreshold Current Relatively high in low threshold devices VDD S G B MP D D G B MN S GND Vo 32
33 Analysis of CMOS circuit power dissipation The power dissipation in a CMOS logic gate can be expressed as P = P static + P dynamic = (VDD I leakage ) + (p f E dynamic ) Where p is the switching probability or activity factor at the output node (i.e. the average number of output switching events per clock cycle). The dynamic energy consumed per output switching event is defined as E dynamic = i DD V 1_ switching_ event DD dt 33
34 Analysis of CMOS circuit power dissipation E dynamic C V L 2 DD 2C M V 2 DD E SC C load V 2 DD [ C dbp C dbn 2( C gdn C gdp )] V The first term the energy dissipation due to the Charging/discharging of the effective load capacitance C L. The second term the energy dissipation due to the inputtooutput coupling capacitance. A rising input results in a V DD  V DD transition of the voltage across C M and so doubles the charge of C M. 2 DD E SC C L = C load + C dbp +C dbn C M = C gdn + C gdp 34
35 The MOSFET parasitic capacitances distributed, voltagedependent, and nonlinear. So their exact modeling is quite complex. Even E SC can be modeled, it is also difficult to calculate the E dynamic. On the other hand, if the shortcircuit current i SC can be Modeled, the powersupply current i DD may be modeled with the same method. So there is a possibility to directly model i DD instead of i SC. 35
36 Schematic of the Inverter 36
37 37
38 Analysis of shortcircuit current The shortcircuit energy dissipation E SC is due to the railtorail current when both the PMOS and NMOS devices are simultaneously on. E SC = E SC_C + E SC_n Where and E E SC_ c SC_ d V V DD DD v v 0 0 V 0 DD i n dt V DD i dt p 0 38
39 Charging and discharging currents Discharging Inverter Charging Inverter 39
40 Factors that affect the shortcircuit current For a longchannel device, assuming that the inverter is symmetrical ( n = p = and V Tn = V Tp = V T ) and with zero load capacitance, and input signal has equal rise and fall times ( r = f = ), the average shortcircuit current [Veendrick, 1994] is I mean 1 12 V 3 ( VDD 2V T ) DD From the above equation, some fundamental factors that affect shortcircuit current are: W ( ), V DD, V T, and T. t ox L T 40
41 Parameters affecting short cct current For a shortchannel device, and VT are no longer constants, but affected by a large number of parameters (i.e. circuit conditions, hspice parameters and process parameters). C L also affects shortcircuit current. I mean is a function of the following parameters (t ox is processdependent): C L,, T (or /T), V DD, W n,p, L n,p (or W n,p / L n,p ), t ox, The above argument is validated by the means of simulation in the case of discharging inverter, 41
42 The effect of C L on Short CCt Current 42
43 Effect of t r on short cct Current 43
44 Effect of Wp on Short cct Current 44
45 Effect of timestep setting on simulation results Tr (ps) Timestep (ps) MaxStep (ps) i Max (ua) i average_int/2 (ua)
46 Thank you! 46
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