Topic 4. The CMOS Inverter


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1 Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: Topic 41
2 Noise in Digital Integrated Circuits Topic 42
3 DC Operation: Voltage Transfer Characteristic Consider a simple inverter When Vin = 0 Vout = Vdd When Vin = Vdd Vout = 0 In between, V out depends on current through transistors as determined by transistor width and length By KCL, steady state condition is: I dsn = I dsp Find transfer function by solving equations, but better insight using graphical method Topic 43
4 DC Transfer Curve: Load line Topic 44
5 DC Transfer Curve Topic 45
6 Operating Regions Topic 46
7 Effect of beta ratio on switching thresholds Extract switching point depends on β p / β n If β p / β n = 1, switching occurs at around Vdd/2 Otherwise: Topic 47
8 Noise Margins Topic 48
9 Maximize Noise Margins Select logic levels at unity gain point of DC transfer characteristic Topic 49
10 Voltage Transfer Characteristic of Real Inverter Topic 410
11 The Regenerative Property Topic 411
12 Delay Definitions Topic 412
13 Ring Oscillator Topic 413
14 Power Dissipation Topic 414
15 Delay Estimation Need to estimate delay without circuit simulation e.g. SPICE Not as accurate as simulation But easier to ask What if? The step response usually looks like a 1 st order RC response with a decaying exponential Use RC delay models to estimate delay C = total capacitance on output node Use effective resistance R so that t pd = RC Characterize transistors by finding their effective R depends on average current as gate switches Topic 415
16 RC Delay Models For each MOS transistor Assume ideal switch + capacitance + ON resistance Unit nmos has resistance R, gate capacitance C Unit pmos has resistance 2R, gate capacitance C Capacitance width ON resistance 1/width Topic 416
17 Computing the Capacitances Topic 417
18 Computing the Capacitances Topic 418
19 Impact of Rise Time on Delay Topic 419
20 Delay as a function of V DD Assuming Vdd = 5V Topic 420
21 Where Does Power Go in CMOS? Dynamic power charging and discharging capacitors Short circuit currents short circuit path between power rails during switching Leakage power Leaking diodes and transistors Topic 421
22 Dynamic Power Dissipation Vdd Vin The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again. Vout C L Energy/transition = C L * V dd 2 Power = Energy/transition * f = C L * V dd 2 * f Not a function of transistor sizes! Need to reduce C L, V dd, and f to reduce power. Topic 422
23 Short Circuit Currents Topic 423
24 Leakage Topic 424
25 SubThreshold in MOS Topic 425
26 How to reduce power? Prime choice: Reduce voltage! Recent years have seen an acceleration in supply voltage reduction Design at very low voltages ( V by 2010!) Maintaining performance by threshold scaling leads to increased leakage Reduce switching activity Reduce physical capacitance Topic 426
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