# EE115C Digital Electronic Circuits Homework #4

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1 EE115 Digital Electronic ircuits Homework #4 Problem 1 Power Dissipation Solution Vdd =1.0V onsider the source follower circuit used to drive a load L =20fF shown above. M1 and M2 are both NMOS transistors parameterized by Table below. V T0 [V] k [μa/v 2 ] γ [V 1/2 ] λ [V 1 ] V DSAT [V] 2Φ F [V] NMOS PMOS a) Assume that the input square wave edges and the inverter are fast compared to the rest of the circuit Solution: The overall function of this circuit is a follower. When VIN is low, M1 is off and M2 is on, and the VOL = 0 V. When VIN is high, M2 is off and M1 is on and in a source follower configuration. As VOUT rises, it eventually reaches VDD - VT, at which point M1 turns off. Therefore, VOH = VDD - VT. However, since V S is not equal to 0, VT is not equal to VT0. We need to find VT from the two equations: A simple way to solve these equations is to iterate with an initial guess for VT:, 1

2 for example, VT = 0.2V. VS = 0.8V VT = V VS = V VT = V VS = V VT = V VS = V VT = V VS = V At this point we are close to the final value, and the last few mv don t affect the solution significantly. Use VOH=0.7608V. Now we can sketch the input and output waveforms: b) What is the power consumption if T=20ns? Neglect the standard inverter and assume that L dominates the device capacitance of M1 and M2. Solution: Note that during a 0 1 transition, we charge the capacitor to VOH, and thus draw an amount of charge Q = LVOH from the supply. Thus, the energy consumed in a single positive transition is E = QVDD = LVDDVOH. Therefore, P = L VDD VOH f0 1 = 20 ff 1V 0.76V 25 MHz. P = 380 nw c) onsider what happens if V IN is not a square wave, but a data stream consisting of a random sequence of bits. If the bit period is 20ns and each bit has an equal chance of being 0 or 1, what is the average power consumption of the circuit? Solution: In this case we use the same power formula as in part (b), but we must determine the new value of f0 1. Since the bits have equal probability of being 0 or 1, every bit has a 50% chance of being different from the previous bit. Thus, on average there is a transition every 40ns. Half of those transitions are 0 1 and half are 1 0, so on average there is a 0 1 transition every 80ns, or f0 1 = 12.5 MHz. P= L VDD VOH f0 1 = 20 ff 1.0V 0.76V 12.5 MHz. P = 190 nw 2

3 Problem 2 FO4 Delay and Switching Energy Dissipation a) FO4 delay: This exercise is similar to calculating FO4 delay from Tutorial 2. Find FO4 Delay of an inverter with following parameters (Wp=650nm, Wn=430nm) when V DD varies from 1V down to 0.15V (50mV increments). Specify capacitance and clock properties as follows: cap : output load, set value to 100f vpulse : (input pulse voltage source) Voltage 1 = 0, Voltage 2 = V DD, Delay time = 100p, Rise time = 10p, Fall time = 10p, Pulse width = 200ps, Period = 400ps b) Energy consumption: Simulate E 0 1 as a function of V DD as V DD varies from 1V down to 0.15V (take V DD step 50mV). To emulate realistic switching cycle in digital logic, set the input switching period to 10 FO4 delay as you scale down V DD. Solution a) For Spectre simulation, we first construct the schematics as the following figure: A Transient Analysis is ran with a pulse input source having the pulse-width of 200ps. The simulation result is shown below. We can use the alculator to measure falling and rising transitions. t PLH = ps, t PHL = ps FO4 _ Delay = ( t + t ) / 2 = 32. ps PLH PHL 81 3

4 b) Let the period of your clock be 40 the FO4 Delay. T = 40 FO4 _ Delay = 1. 32ns Find switching energy dissipation. 250 ps 14 E = Vdd i( t) dt = 1 i( t) dt = ps You can again use the alculator to find the integration of current. This step can be done while varying Vdd. Following table and figure illustrate how energy dissipation changes with Vdd. Note that near Subthreshold region, you need to allow sufficient about of time for the logic to charge and discharge. 4

5 Vdd Isw[A*T] Esw[fJ] t plh t phl tp ps 29.23ps 33.60ps ps 31.07ps 36ps ps 33.28ps 38ps ps 36.1ps 42ps ps 39.51ps 45ps ps 43.85ps 50.5ps ps 49.57ps 57ps ps 57.23ps 65ps ps 68ps 72ps ps 84.04ps 95ps ,.9ps 110.3ps 125ps ps 158.6ps 178ps ps 270ps 293.5ps ps 515.8ps 566ps ns 1.2ns 1.3ns ns 3.185n 3.7ns ns 9.3ns 14ns 5

6 Problem 3 MOS Gate Design Electrical Engineering Department Spring 2010 a) Design F = A + A +. b) apacitance of internal nodes = int, apacitance of loading = L, Resistance of NMOS = R N, Resistance of PMOS = R P, calculate t phl and t plh for all possible input combinations (hint: for a first-order estimate, ignore int ). Solution a) One possible implementation: A F A 2x b) List the Truth Table and use delay = 0.69R for pull-down or pull-up network. For example: If {A,, }={0, 1, 1} F = 0, equivalent pull-down resistance = 2R N t phl = R N. L = 1.38 R N L A F t phl t plh R P L R P L R P L R N L R P L R N L R N L R N L - 6

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