Last Lecture. Power Dissipation CMOS Scaling. EECS 141 S02 Lecture 8


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1 EECS 141 S02 Lecture 8 Power Dissipation CMOS Scaling Last Lecture CMOS Inverter loading Switching Performance Evaluation Design optimization Inverter Sizing 1
2 Today CMOS Inverter power dissipation» Dynamic» ShortCircuit» Leakage Scaling CMOS into the future Power Dissipation 2
3 Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking diodes and transistors Dynamic Power Dissipation Vdd Vin Vout C L Energy/transition = C L * V dd 2 Power = Energy/transition * f = C L * V dd 2 * f Not a function of transistor sizes! Need to reduce C L, V dd, and f to reduce power. 3
4 Modification for Circuits with Reduced Swing V dd V dd V dd V t C L E 0 1 = C L V dd ( V dd V t ) Can exploit reduced swing to lower power (e.g., reduced bitline swing in memory) Adiabatic Charging
5 Adiabatic Charging Node Transition Activity and Power Consider switching a CMOS gate for N clock cycles E N = C L V 2 dd nn ( ) E N : the energy consumed for N clock cycles n(n): the number of 0>1 transition in N clock cycles P avg = lim N E N f N clk = nn ( ) lim C V N N dd fclk L α 0 1 = nn ( ) lim N N P avg = α 0 1 C L V 2 fclk dd 5
6 Transistor Sizing for Minimum Energy In Out C g1 1 f C ext Goal: Minimize Energy of whole circuit» Design parameters: f and V DD» tp tpref of circuit with f=1 and V DD =V ref t t p p0 f = t p γ VDD V V DD TE F fγ Transistor Sizing (2) Performance Constraint (γ=1) t t p pref t = t p0 p0ref 2 + f + F f V = ( 3+ F ) V V V ( 3+ F ) Energy for single Transition E = V E E ref 2 DD C V = V g1 DD ref V 2 + f + = 1 DD ref V ref DD TE TE [( 1+ γ )( 1+ f ) + F ] f + F 4 + F F f 6
7 Transistor Sizing (3) V DD =f(f) E/E ref =f(f) vdd (V) F= normalized energy f f Short Circuit Currents Vdd Vin Vout C L 0.15 IVDD (ma) V in (V)
8 How to keep ShortCircuit Currents Down? Short circuit current goes to zero if t fall >> t rise, but can t do this for cascade logic, so... Minimizing ShortCircuit Power Vdd =3.3 P norm 5 4 Vdd = Vdd = t sin /t sout 8
9 Leakage Vdd Vout Drain Junction Leakage SubThreshold Current Subthreshold current one of most compelling issues in lowenergy circuit design! ReverseBiased Diode Leakage GATE p + p+ N +  V dd Reverse Leakage Current I DL = J S A JS = pa/µm2 at 25 deg C for 0.25µm CMOS JS doubles for every 9 deg C! 9
10 Subthreshold Leakage Component Static Power Consumption Vdd I stat V out V in =5V C L P stat = P (In=1).V dd. I stat Wasted energy Should be avoided in most cases, but could help reducing energy in others (e.g. sense amps) 10
11 Principles for Power Reduction Prime choice: Reduce voltage!» Recent years have seen an acceleration in supply voltage reduction» Design at very low voltages still open question ( V by 2010!) Reduce switching activity Reduce physical capacitance» Device Sizing: for F=20 f opt (energy)=3.53, f opt (performance)=4.47 Impact of Technology Scaling 11
12 Goals of Technology Scaling Make things cheaper:» Want to sell more functions (transistors) per chip for the same money» Build same products cheaper, sell the same part for less money» Price of a transistor has to be reduced But also want to be faster, smaller, lower power Technology Scaling Goals of scaling the dimensions by 30%:» Reduce gate delay by 30% (increase operating frequency by 43%)» Double transistor density» Reduce energy per transition by 65% (50% power 43% increase in frequency Die size used to increase by 14% per generation Technology generation spans 23 years 12
13 Technology Evolution (2000 data) International Technology Roadmap for Semiconductors Year of Introduction Technology node [nm] Supply [V] Wiring levels Max frequency [GHz],LocalGlobal Max µp power [W] Bat. power [W] Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm Technology Evolution (1999) 13
14 ITRS Technology Roadmap Acceleration Continues Technology Scaling (1) Minimum Feature Size (micron) Year Minimum Feature Size 14
15 Technology Scaling (2) Number of components per chip Technology Scaling (3) t p decreases by 13%/year 50% every 5 years! Propagation Delay 15
16 Technology Scaling (4) 100 x1.4 / 3 years 1000 κ 0.7 Power Dissipation (W) x4 / 3 years 85 (a) Power dissipation vs. year. 90 Year MPU DSP 95 Power Density (mw/mm 2 ) κ Scaling Factor κ i normalized by 4µm design rule j (b) Power density vs. scaling factor. 10 From Kuroda Technology Scaling Models Full Scaling (Constant Electrical Field) ideal model dimensions and voltage scale together by the same factor S Fixed Voltage Scaling most common model until recently only dimensions scale, voltages remain constant General Scaling most realistic for todays situation voltages and dimensions scale with different factors 16
17 Scaling Relationships for Long Channel Devices Transistor Scaling (velocitysaturated devices) 17
18 µprocessor Scaling P.Gelsinger: µprocessors for the New Millenium, ISSCC 2001 µprocessor Power P.Gelsinger: µprocessors for the New Millenium, ISSCC
19 µprocessor Performance P.Gelsinger: µprocessors for the New Millenium, ISSCC Outlook Performance 2X/16 months» 1 TIP (terra instructions/s)» 30 GHz clock Size» No of transistors: 2 Billion» Die: 40*40 mm Power» 10kW!!» Leakage: 1/3 active Power P.Gelsinger: µprocessors for the New Millenium, ISSCC
20 Some interesting questions What will cause this model to break? When will it break? Will the model gradually slow down?» Power and power density» Leakage» Process Variation 20
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