VLSI Design I; A. Milenkovic 1


 Noah Hubbard
 3 years ago
 Views:
Transcription
1 Why Power Matters PE/EE 47, PE 57 VLSI Design I L5: Power and Designing for Low Power Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( ) Packaging costs Power supply rail design hip and system cooling costs Noise immunity and system reliability attery life (in portable systems) Environmental concerns Office equipment accounted for 5% of total US commercial energy usage in 993 Star compliant systems /8/5 VLSI Design I;. Milenkovic Why worry about power?  Power Dissipation Problem Illustration Lead microprocessors power continues to increase P6 Pentium Power (Watts) Year Power delivery and dissipation will be prohibitive Source: orkar, De Intel /8/5 VLSI Design I;. Milenkovic 3 /8/5 VLSI Design I;. Milenkovic 4 attery (4+ lbs) Why worry about power? attery Size/Weight Nominal apacity (Whr/lb) Expected battery lifetime increase over the next 5 years: 3 to 4% Rechargable Lithium Nickeladmium NiMetal Hydride Year From Rabaey,, 995 /8/5 VLSI Design I;. Milenkovic 5 Why worry about power?  Standby Power Drain leakage will increase as V T decreases to maintain noise margins and meet frequency demands, leading to excessive battery draining standby power consumption. 8KW Standby Power Year Power supply V dd (V) Threshold V T (V) 5% 4% 3% % % W 88W.5.4 4W KW % Source: orkar, De Intel /8/5 VLSI Design I;. Milenkovic and phones leaky! VLSI Design I;. Milenkovic
2 better better Power and Figures of Merit Power consumption in Watts determines battery life in hours Peak power determines power ground wiring designs sets packaging limits impacts signal noise margin and reliability analysis efficiency in Joules rate at which power is consumed over time = power * delay Joules = Watts * seconds lower energy number means less power to perform a computation at the same frequency Watts Watts Power versus Power is height of curve Lower power design could simply be slower pproach pproach time is area under curve Two approaches require the same energy pproach pproach time /8/5 VLSI Design I;. Milenkovic 7 /8/5 VLSI Design I;. Milenkovic 8 PDP and EDP Powerdelay product (PDP) = P av * t p = ( )/ PDP is the average energy consumed per switching event (Watts * sec = Joule) lower power design could simply be a slower design delay product (EDP) = PDP * t p = P av * t p 5 EDP is the average energy energydelay consumed multiplied by the computation time required takes into account that one can trade increased delay energy for lower energy/operation 5 (e.g., via supply voltage scaling that increases delay, delay but decreases energy consumption).5 allows one to understand tradeoffs better.5.5 Vdd (V) /8/5 VLSI Design I;. Milenkovic 9 Delay (normalized) Understanding Tradeoffs Which design is the best (fastest, coolest, both)? b c a d /Delay better /8/5 VLSI Design I;. Milenkovic Understanding Tradeoffs MOS & Power Equations Which design is the best (fastest, coolest, both)? E = P + t sc I peak P + I leakage d b c a Lower EDP f = P * f clock P = f + t sc I peak f + I leakage /Delay better /8/5 VLSI Design I;. Milenkovic Dynamic power Shortcircuit power Leakage power /8/5 VLSI Design I;. Milenkovic VLSI Design I;. Milenkovic
3 Dynamic Power onsumption Vdd Vin Pop Quiz onsider a.5 micron chip, 5 MHz clock, average load cap of 5fF/gate (fanout of 4),.5V supply. Dynamic Power consumption per gate is?? /transition = * * P P dyn = /transition * f = * * P * f P dyn = EFF * * f where EFF = P Not a function of transistor sizes! Data dependent  a function of switching activity! f /8/5 VLSI Design I;. Milenkovic 3 With million gates (assuming each transitions every clock) Dynamic Power of entire chip =??. /8/5 VLSI Design I;. Milenkovic 4 Lowering Dynamic Power Short ircuit Power onsumption apacitance: Function of fanout, wire length, transistor sizes Supply Voltage: Has been dropping with successive generations Vin I sc P dyn = P f ctivity factor: How often, on average, do wires switch? lock frequency: Increasing Finite slope of the input signal causes a direct current path between and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting. /8/5 VLSI Design I;. Milenkovic 5 /8/5 VLSI Design I;. Milenkovic 6 Short ircuit urrents Determinates Impact of on P sc E sc = t sc I peak P I sc I sc I max P sc = t sc I peak f Vin Vin Duration and slope of the input signal, t sc I peak determined by the saturation current of the P and N transistors which depend on their sizes, process technology, temperature, etc. strong function of the ratio between input and output slopes a function of Large capacitive load Output fall time significantly larger than input rise time. Small capacitive load Output fall time substantially smaller than the input rise time. /8/5 VLSI Design I;. Milenkovic 7 /8/5 VLSI Design I;. Milenkovic 8 VLSI Design I;. Milenkovic 3
4 I peak () x I peak as a Function of = ff = ff = 5 ff 4 6 x time (sec) 5 psec input slope When load capacitance is small, I peak is large. Short circuit dissipation is minimized by matching the rise/fall times of the input and output signals  slope engineering. /8/5 VLSI Design I;. Milenkovic 9 P normalized P sc as a Function of Rise/Fall Times = 3.3 V =.5 V =.5V When load capacitance is small (t sin /t sout > for > V) the power is dominated by P sc If < V Tn + V Tp then P sc is eliminated since both devices are never on at the same time. t sin /t sout 4 W/L p =.5 µm/.5 µm normalized wrt zero input W/L n =.375 µm/.5 µm risetime dissipation = 3 ff /8/5 VLSI Design I;. Milenkovic Leakage (Static) Power onsumption Gate leakage I leakage Drain junction leakage Subthreshold current Subthreshold current is the dominant factor. ll increase exponentially with temperature! /8/5 VLSI Design I;. Milenkovic  ID () 7 Leakage as a Function of V T ontinued scaling of supply voltage and the subsequent scaling of threshold voltage will make subthreshold conduction a dominant component of power dissipation. VT=.4V VT=.V n 9mV/decade V T rolloff  so each 55mV increase in V T gives 3 orders of magnitude reduction in leakage (but adversely affects performance) VGS (V) /8/5 VLSI Design I;. Milenkovic TSM Processes Leakage and V T Exponential Increase in Leakage urrents V dd T ox (effective) L gate I DSat (n/p) (µ/µm) I off (leakage) (ρ/µm) V Tn FET Perf. (GHz) L8 G.8 V 4 Å.6 µm 6/6.4 V 3 L8 LP.8 V 4 Å.6 µm 5/ V L8 ULP.8 V 4 Å.8 µm 3/ V 4 L8 HS V 4 Å.3 µm 78/ V 43 L5 HS.5 V 9 Å. µm 86/37,8.9 V 5 L3 HS. V 4 Å.8 µm 9/4 3,.5 V 8 I leakage (n/µm) Temp() From MPR, /8/5 VLSI Design I;. Milenkovic 3 From De,999 /8/5 VLSI Design I;. Milenkovic 4 VLSI Design I;. Milenkovic 4
5 Review: & Power Equations Power and Design Space E = P I leakage + t sc I peak P + P = f + t sc I peak f + Dynamic power (~9% today and decreasing relatively) f = P * f clock Shortcircuit power (~8% today and decreasing absolutely) I leakage Leakage power (~% today and increasing) ctive Leakage onstant Design Time Logic Design Reduced V dd Sizing + MultiV T Nonactive Modules lock Gating Sleep Transistors Variable V T Variable Run Time DFS, DVS (Dynamic Freq, Voltage Scaling) + Variable V T /8/5 VLSI Design I;. Milenkovic 5 /8/5 VLSI Design I;. Milenkovic 6 Dynamic Power as a Function of Device Size Device sizing affects dynamic energy consumption gain is largest for networks with large overall effective fanouts (F = / g, ) The optimal gate sizing.5 factor (f) for dynamic energy F= is smaller than the one for performance, especially for F= large F s F=5 e.g., for F=, f opt (energy) = 3.53 while f opt (performance) = 4.47 If energy is a concern avoid oversizing beyond the optimal From Nikolic, U /8/5 VLSI Design I;. Milenkovic 7 normalized energy.5 f F= F= Dynamic Power onsumption is Data Dependent Switching activity, P, has two components static component function of the logic topology dynamic component function of the timing behavior (glitching) Static transition probability P = P out= x P out= input NOR Gate = P Out x (P ) With input signal probabilities P = = / P = = / NOR static transition probability = 3/4 x /4 = 3/6 /8/5 VLSI Design I;. Milenkovic 8 NOR Gate Transition Probabilities Switching activity is a strong function of the input signal statistics P and P are the probabilities that inputs and are one P P = P x P = ((P )(P )) (P )(P ) /8/5 VLSI Design I;. Milenkovic 9 P Transition Probabilities for Some asic Gates P = P out= x P out= NOR ((P )(  P )) x (  P )(  P ) OR (  P )(  P ) x ((P )(  P )) NND P P x (  P P ) ND (  P P ) x P P OR (  (P + P P P )) x (P + P P P ).5.5 For : P = For : P = /8/5 VLSI Design I;. Milenkovic 3 VLSI Design I;. Milenkovic 5
6 Transition Probabilities for Some asic Gates NOR OR NND P = P out= x P out= ((P )(  P )) x (  P )(  P ) (  P )(  P ) x ( ( P )(  P )) P P x (  P P ) ND (  P P ) x P P OR (  (P + P P P )) x (P + P P P ).5.5 For : P = P x P = (P ) P =.5 x.5 =.5 For : P = P x P = (P P ) P P = ( (.5 x.5)) x (.5 x.5) = 3/6 /8/5 VLSI Design I;. Milenkovic 3 Intersignal orrelations Determining switching activity is complicated by the fact that signals exhibit correlation in space and time reconvergent fanout.5.5 Reconvergent fanout P(=) = P(=) & P(= =) Have to use conditional probabilities /8/5 VLSI Design I;. Milenkovic Intersignal orrelations Determining switching activity is complicated by the fact that signals exhibit correlation in space and time reconvergent fanout (.5)(.5)x((.5)(.5)) = 3/6 P(=) = P(=) * P(= =) =.5 * =.5 Reconvergent P(=) = P(=)*P(= =) =.5 P(>) =.5*.5 =.5 P(=) = P(=) & P(= =) Have to use conditional probabilities Logic Restructuring Logic restructuring: changing the topology of a logic network to reduce transitions ND: P = P x P = (  P P ) x P P.5.5 (.5)*.5 = 3/6 W 7/64.5 5/ D F D.5.5 3/6 Y 3/6 hain implementation has a lower overall switching activity than the tree implementation for random inputs Ignores glitching effects 5/56 F /8/5 VLSI Design I;. Milenkovic 33 /8/5 VLSI Design I;. Milenkovic 34 Input Ordering Input Ordering.5.. F...5 F.5. (.5x.)x(.5x.)=.9 F. (.x.)x(.x.)=.96.. F.5 eneficial to postpone the introduction of signals with a high transition rate (signals with signal probability close to.5) eneficial to postpone the introduction of signals with a high transition rate (signals with signal probability close to.5) /8/5 VLSI Design I;. Milenkovic 35 /8/5 VLSI Design I;. Milenkovic 36 VLSI Design I;. Milenkovic 6
7 Glitching in Static MOS Networks Gates have a nonzero propagation delay resulting in spurious transitions or glitches (dynamic hazards) glitch: node exhibits multiple transitions in a single cycle before settling to the correct logic value Glitching in Static MOS Networks Gates have a nonzero propagation delay resulting in spurious transitions or glitches (dynamic hazards) glitch: node exhibits multiple transitions in a single cycle before settling to the correct logic value Unit Delay /8/5 VLSI Design I;. Milenkovic 37 Unit Delay /8/5 VLSI Design I;. Milenkovic 38 Glitching in an R in S5 S4 S S S 3 S Output Voltage (V) S3 S4 S5 in S S5 S S S /8/5 VLSI Design Time I;. (ps) Milenkovic 39 alanced Delay Paths to Reduce Glitching Glitching is due to a mismatch in the path lengths in the logic network; if all input signals of a gate change simultaneously, no glitching occurs F F F 3 So equalize the lengths of timing paths through logic /8/5 VLSI Design I;. Milenkovic 4 F F F 3 Power and Design Space Dynamic Power as a Function of ctive Leakage onstant Design Time Logic Design Reduced V dd Sizing + MultiV T Nonactive Modules lock Gating Sleep Transistors Variable V T Variable Run Time DFS, DVS (Dynamic Freq, Voltage Scaling) + Variable V T Decreasing the decreases dynamic energy consumption (quadratically) ut, increases gate delay (decreases performance) t p(normalized) (V) Determine the critical path(s) at design time and use high for the transistors on those paths for speed. Use a lower on the other gates, especially those that drive large capacitances (as this yields the largest energy benefits). /8/5 VLSI Design I;. Milenkovic 4 /8/5 VLSI Design I;. Milenkovic 4 VLSI Design I;. Milenkovic 7
8 Multiple onsiderations How many? Two is becoming common Many chips already have two supplies (one for core and one for I/O) When combining multiple supplies, level converters are required whenever a module at the lower supply drives a gate at the higher supply (stepup) If a gate supplied with L drives a gate at H, the PMOS never turns off H The crosscoupled PMOS transistors do the level conversion The NMOS transistor operate on a V out VDDL reduced supply V in Level converters are not needed for a stepdown change in voltage Overhead of level converters can be mitigated by doing conversions at register boundaries and embedding the level conversion inside the flipflop /8/5 VLSI Design I;. Milenkovic 43 DualSupply Inside a Logic lock Minimum energy consumption is achieved if all logic paths are critical (have the same delay) lustered voltagescaling Each path starts with H and switches to L (gray logic gates) when delay slack is available Level conversion is done in the flipflops at the end of the paths /8/5 VLSI Design I;. Milenkovic 44 ctive Leakage Power and Design Space onstant Design Time Logic Design Reduced V dd Sizing + MultiV T Nonactive Modules lock Gating Sleep Transistors Variable V T Variable Run Time DFS, DVS (Dynamic Freq, Voltage Scaling) + Variable V T /8/5 VLSI Design I;. Milenkovic 45 Stack Effect Leakage is a function of the circuit topology and the value of the inputs V T = V T + γ( φ F + V S  φ F ) where V T is the threshold voltage at V S = ; V S is the sourcebulk (substrate) voltage; γ is the bodyeffect coefficient V V T ln(+n) V GS =V S = V Out V GS =V S = V T V GS =V S = V V SG =V S = /8/5 VLSI Design I;. Milenkovic 46 I SU Leakage is least when = = Leakage reduction due to stacked transistors is called the stack effect Short hannel Factors and Stack Effect In shortchannel devices, the subthreshold leakage current depends on V GS,V S and V DS. The V T of a shortchannel device decreases with increasing V DS due to DIL (draininduced barrier loading). Typical values for DIL are to 5mV change in V T per voltage change in V DS so the stack effect is even more significant for shortchannel devices. V reduces the drainsource voltage of the top nfet, increasing its V T and lowering its leakage For our.5 micron technology, V settles to ~mv in steady state so V S = mv and V DS = mv which is times smaller than the leakage of a device with V S = mv and V DS = Leakage as a Function of Design Time V T Reducing the V T increases the subthreshold leakage current (exponentially) 9mV reduction in V T increases leakage by an order of magnitude ut, reducing V T decreases gate delay (increases performance) ID () VT=.4V VT=.V VGS (V) Determine the critical path(s) at design time and use low V T devices on the transistors on those paths for speed. Use a high V T on the other logic for leakage control. careful assignment of V T s can reduce the leakage by as much as 8% /8/5 VLSI Design I;. Milenkovic 47 /8/5 VLSI Design I;. Milenkovic 48 VLSI Design I;. Milenkovic 8
9 V T (V) DualThresholds Inside a Logic lock Variable V T () at Run Time Minimum energy consumption is achieved if all logic paths are critical (have the same delay) Use lower threshold on timingcritical paths ssignment can be done on a per gate or transistor basis; no clustering of the logic is needed No level converters are needed /8/5 VLSI Design I;. Milenkovic 49 V T = V T + γ( φ F + V S  φ F ) For an nchannel device, the substrate is normally tied to ground (V S = ) negative bias on V S causes V T to increase djusting the substrate bias at run time is called adaptive bodybiasing () Requires a dual well fab process V S (V) /8/5 VLSI Design I;. Milenkovic VLSI Design I;. Milenkovic 9
CSE493/593. Designing for Low Power
CSE493/593 Designing for Low Power Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.].1 Why Power Matters Packaging costs Power supply rail design Chip and system
More informationEECS 427 Lecture 11: Power and Energy Reading: EECS 427 F09 Lecture Reminders
EECS 47 Lecture 11: Power and Energy Reading: 5.55 [Adapted from Irwin and Narayanan] 1 Reminders CAD5 is due Wednesday 10/8 You can submit it by Thursday 10/9 at noon Lecture on 11/ will be taught by
More informationCMPEN 411 VLSI Digital Circuits Spring Lecture 14: Designing for Low Power
CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 14: Designing for Low Power [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp12 CMPEN
More informationASIC FPGA Chip hip Design Pow Po e w r e Di ssipation ssipa Mahdi Shabany
ASIC/FPGA Chip Design Power Di ssipation Mahdi Shabany Department tof Electrical ti lengineering i Sharif University of technology Outline Introduction o Dynamic Power Dissipation Static Power Dissipation
More informationEE115C Winter 2017 Digital Electronic Circuits. Lecture 6: Power Consumption
EE115C Winter 2017 Digital Electronic Circuits Lecture 6: Power Consumption Four Key Design Metrics for Digital ICs Cost of ICs Reliability Speed Power EE115C Winter 2017 2 Power and Energy Challenges
More informationPower Dissipation. Where Does Power Go in CMOS?
Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit
More informationLecture 81. Low Power Design
Lecture 8 Konstantinos Masselos Department of Electrical & Electronic Engineering Imperial College London URL: http://cas.ee.ic.ac.uk/~kostas Email: k.masselos@ic.ac.uk Lecture 81 Based on slides/material
More informationMODULE III PHYSICAL DESIGN ISSUES
VLSI Digital Design MODULE III PHYSICAL DESIGN ISSUES 3.2 Powersupply and clock distribution EE  VDD P2006 3:1 3.1.1 Power dissipation in CMOS gates Power dissipation importance Package Cost. Power
More informationEE241  Spring 2000 Advanced Digital Integrated Circuits. Announcements
EE241  Spring 2 Advanced Digital Integrated Circuits Lecture 11 Low PowerLow Energy Circuit Design Announcements Homework #2 due Friday, 3/3 by 5pm Midterm project reports due in two weeks  3/7 by 5pm
More informationProperties of CMOS Gates Snapshot
MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)
More informationDynamic operation 20
Dynamic operation 20 A simple model for the propagation delay Symmetric inverter (rise and fall delays are identical) otal capacitance is linear t p Minimum length devices R W C L t = 0.69R C = p W L 0.69
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 8 Power Dissipation in CMOS Gates Power in CMOS gates Dynamic Power Capacitance switching Crowbar
More informationCMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
More informationCPE/EE 427, CPE 527 VLSI Design I Pass Transistor Logic. Review: CMOS Circuit Styles
PE/EE 427, PE 527 VLI Design I Pass Transistor Logic Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: MO ircuit
More informationObjective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components
Objective: Power Components Outline: 1) Acknowledgements 2) Objective and Outline 1 Acknowledgement This lecture note has been obtained from similar courses all over the world. I wish to thank all the
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More informationCPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look
CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates epartment of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka )
More informationDigital Integrated Circuits A Design Perspective
Designing ombinational Logic ircuits dapted from hapter 6 of Digital Integrated ircuits Design Perspective Jan M. Rabaey et al. opyright 2003 Prentice Hall/Pearson 1 ombinational vs. Sequential Logic In
More informationEE241  Spring 2001 Advanced Digital Integrated Circuits
EE241  Spring 21 Advanced Digital Integrated Circuits Lecture 12 Low Power Design SelfResetting Logic Signals are pulses, not levels 1 SelfResetting Logic SenseAmplifying Logic Matsui, JSSC 12/94 2
More informationCMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties.
CMOS Inverter: Steady State Response CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates R p V OL = V OH = V M = f(r n, R p ) epartment of Electrical and Computer Engineering University
More informationAnnouncements. EE141 Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power
 Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 123pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances
More informationLecture 2: CMOS technology. Energyaware computing
EnergyAware Computing Lecture 2: CMOS technology Basic components Transistors Two types: NMOS, PMOS Wires (interconnect) Transistors as switches Gate Drain Source NMOS: When G is @ logic 1 (actually over
More informationWhere Does Power Go in CMOS?
Power Dissipation Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking
More information9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design
More informationLecture 6 Power Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010
EE4800 CMOS Digital IC Design & Analysis Lecture 6 Power Zhuo Feng 6.1 Outline Power and Energy Dynamic Power Static Power 6.2 Power and Energy Power is drawn from a voltage source attached to the V DD
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler
More informationCMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
More informationMiscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]
Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an NSwitch, the
More informationMidterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More informationLecture 4: CMOS review & Dynamic Logic
Lecture 4: CMOS review & Dynamic Logic Reading: ch5, ch6 Overview CMOS basics Power and energy in CMOS Dynamic logic 1 CMOS Properties Full railtorail swing high noise margins Logic levels not dependent
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 14 The CMOS Inverter: dynamic behavior (sizing, inverter
More informationCPE/EE 427, CPE 527 VLSI Design I L07: CMOS Logic Gates, Pass Transistor Logic. Review: CMOS Circuit Styles
PE/EE 427, PE 527 VLI esign I L07: MO Logic Gates, Pass Transistor Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka
More informationENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)
ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More informationDigital Integrated Circuits A Design Perspective
igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational
More informationCPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville
CPE/EE 47, CPE 57 VLSI Design I Delay Estimation Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: CMOS Circuit
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NORgate C = NOT (A or B)
1 Introduction to TransistorLevel Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationDesign for Manufacturability and Power Estimation. Physical issues verification (DSM)
Design for Manufacturability and Power Estimation Lecture 25 Alessandra Nardi Thanks to Prof. Jan Rabaey and Prof. K. Keutzer Physical issues verification (DSM) Interconnects Signal Integrity P/G integrity
More informationCPE/EE 427, CPE 527 VLSI Design I L18: Circuit Families. Outline
CPE/EE 47, CPE 57 VLI Design I L8: Circuit Families Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe5705f
More informationEEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this
More informationMASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences
MSSCHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences nalysis and Design of Digital Integrated Circuits (6.374)  Fall 2003 Quiz #1 Prof. nantha Chandrakasan Student
More informationB.Supmonchai July 5th, q Quantification of Design Metrics of an inverter. q Optimization of an inverter design. B.Supmonchai Why CMOS Inverter?
July 5th, 4 Goals of This Chapter Quantification of Design Metrics of an inverter Static (or SteadyState) Behavior Chapter 5 CMOS Inverter Boonchuay Supmonchai Integrated Design Application Research (IDAR)
More informationIntroduction to CMOS VLSI Design (E158) Lecture 20: Low Power Design
Harris Introduction to CMOS VLSI Design (E158) Lecture 20: Low Power Design David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University MAH E158
More informationEEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture. Rajeevan Amirtharajah University of California, Davis
EEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture Rajeevan Amirtharajah University of California, Davis Outline Announcements Review: PDP, EDP, Intersignal Correlations, Glitching, Top
More informationEE115C Digital Electronic Circuits Homework #4
EE115 Digital Electronic ircuits Homework #4 Problem 1 Power Dissipation Solution Vdd =1.0V onsider the source follower circuit used to drive a load L =20fF shown above. M1 and M2 are both NMOS transistors
More informationCOMP 103. Lecture 16. Dynamic Logic
COMP 03 Lecture 6 Dynamic Logic Reading: 6.3, 6.4 [ll lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP03
More informationCMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic [dapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey,. Chandrakasan,. Nikolic] Sp11 CMPEN 411
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models MOS
More informationENEE 359a Digital VLSI Design
SLIDE 1 ENEE 359a Digital VLSI Design Prof. blj@eng.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay s CSE477 slides
More informationEE141. Administrative Stuff
Spring 2004 Digital Integrated ircuits Lecture 15 Logical Effort Pass Transistor Logic 1 dministrative Stuff First (short) project to be launched next Th. Overall span: 1 week Hardware lab this week Hw
More informationThe Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two
More informationECE321 Electronics I
ECE31 Electronics Lecture 1: CMOS nverter: Noise Margin & Delay Model Payman ZarkeshHa Office: ECE Bldg. 30B Office hours: Tuesday :003:00PM or by appointment Email: payman@ece.unm.edu Slide: 1 CMOS
More information5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1
5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design
More informationEEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW
More informationEE241  Spring 2005 Advanced Digital Integrated Circuits. Admin. Lecture 10: Power Intro
EE241  Spring 2005 Advanced Digital Integrated Circuits Lecture 10: Power Intro Admin Project Phase 2 due Monday March 14, 5pm (by email to jan@eecs.berkeley.edu and huifangq@eecs.berkeley.edu) Should
More information! Energy Optimization. ! Design Space Exploration. " Example. ! P tot P static + P dyn + P sc. ! SteadyState: V in =V dd. " PMOS: subthreshold
ESE 570: igital Integrated ircuits and VLSI undamentals Lec 17: March 26, 2019 Energy Optimization & esign Space Exploration Lecture Outline! Energy Optimization! esign Space Exploration " Example 3 Energy
More informationVLSI Design I; A. Milenkovic 1
ourse dministration PE/EE 47, PE 57 VLI esign I L6: tatic MO Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www. ece.uah.edu/~milenka )
More informationUniversity of Toronto. Final Exam
University of Toronto Final Exam Date  Apr 18, 011 Duration:.5 hrs ECE334 Digital Electronics Lecturer  D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
More informationVLSI Design I; A. Milenkovic 1
PE/EE 47, PE 57 VLI esign I L6: tatic MO Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www. ece.uah.edu/~milenka ) www. ece.uah.edu/~milenka/cpe573f
More informationLast Lecture. Power Dissipation CMOS Scaling. EECS 141 S02 Lecture 8
EECS 141 S02 Lecture 8 Power Dissipation CMOS Scaling Last Lecture CMOS Inverter loading Switching Performance Evaluation Design optimization Inverter Sizing 1 Today CMOS Inverter power dissipation» Dynamic»
More informationL16: Power Dissipation in Digital Systems. L16: Spring 2007 Introductory Digital Systems Laboratory
L16: Power Dissipation in Digital Systems 1 Problem #1: Power Dissipation/Heat Power (Watts) 100000 10000 1000 100 10 1 0.1 4004 80088080 8085 808686 386 486 Pentium proc 18KW 5KW 1.5KW 500W 1971 1974
More informationDelay and Power Estimation
EEN454 Digital Integrated ircuit Design Delay and Power Estimation EEN 454 Delay Estimation We would like to be able to easily estimate delay Not as accurate as simulation But make it easier to ask What
More informationVLSI Design I; A. Milenkovic 1
ourse dministration PE/EE 47, PE 57 VLI esign I L6: omplementary MO Logic Gates epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka
More informationVLSI Design I; A. Milenkovic 1
Review Voltage wing of PT Driving an Inverter PE/EE 47, PE 57 VLI Design I L9: MO & Wire apacitances Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic
More informationDigital Microelectronic Circuits ( ) The CMOS Inverter. Lecture 4: Presented by: Adam Teman
Digital Microelectronic Circuits (3611301 ) Presented by: Adam Teman Lecture 4: The CMOS Inverter 1 Last Lectures Moore s Law Terminology» Static Properties» Dynamic Properties» Power The MOSFET Transistor»
More informationChapter 5. The Inverter. V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov Inverter
Chapter 5 The Inverter V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov.12 03 Objective of This Chapter Use Inverter to know basic CMOS Circuits Operations Watch for performance Index such as Speed (Delay calculation)
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 9 Propagation delay Power and delay Tradeoffs Follow board notes Propagation Delay Switching Time
More informationEECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 111:3 Thursday, October 6, 6:38:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 16 CMOS Combinational Circuits  2 guntzel@inf.ufsc.br
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationCMOS Technology for Computer Architects
CMOS Technology for Computer Architects Recap Technology Trends Lecture 2: Transistor Inverter Iakovos Mavroidis Giorgos Passas Manolis Katevenis FORTHICS (University of Crete) 1 2 Recap Threshold Voltage
More informationToday s lecture. EE141 Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
 Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
More informationEE5311 Digital IC Design
EE5311 Digital IC Design Module 3  The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 3, 2018 Janakiraman, IITM
More informationMOS Transistor IV Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor IV Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationDigital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationCOMBINATIONAL LOGIC. Combinational Logic
COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino npcmos Combinational vs. Sequential Logic In Logic
More informationEEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 8 Lecture #5: CMOS Inverter AC Characteristics Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Acknowledgments Slides due to Rajit Manohar from ECE 547 Advanced
More information2007 Fall: Electronic Circuits 2 CHAPTER 10. DeogKyoon Jeong School of Electrical Engineering
007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits DeogKyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Restore Output. Pass Transistor Logic. How compare.
ESE 570: igital Integrated ircuits and VLSI undamentals Lec 16: March 19, 2019 Euler Paths and Energy asics & Optimization Lecture Outline! Pass Transistor Logic! Logic omparison! Transmission Gates! Euler
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationEEE 421 VLSI Circuits
EEE 421 CMOS Properties Full railtorail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady
More informationDC and Transient Responses (i.e. delay) (some comments on power too!)
DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02  CMOS Transistor Theory & the Effects of Scaling
More informationBased on slides/material by. Topic 34. Combinational Logic. Outline. The CMOS Inverter: A First Glance
ased on slides/material by Topic 3 J. Rabaey http://bwrc.eecs.berkeley.edu/lasses/icook/instructors.html Digital Integrated ircuits: Design Perspective, Prentice Hall D. Harris http://www.cmosvlsi.com/coursematerials.html
More informationSpiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp
27.1 Spiral 2 7 Capacitance, Delay and Sizing Mark Redekopp 27.2 Learning Outcomes I understand the sources of capacitance in CMOS circuits I understand how delay scales with resistance, capacitance
More informationENEE 359a Digital VLSI Design
SLIDE 1 ENEE 359a Digital VLSI Design & Logical Effort Prof. blj@ece.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor NChannel MOSFET Built on ptype
More informationDigital Integrated Circuits
Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Shortcircuit current The CMOS inverter :
More informationChapter 8. LowPower VLSI Design Methodology
VLSI Design hapter 8 LowPower VLSI Design Methodology JinFu Li hapter 8 LowPower VLSI Design Methodology Introduction LowPower GateLevel Design LowPower ArchitectureLevel Design AlgorithmicLevel
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationCMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering
CMOS logic gates João Canas Ferreira University of Porto Faculty of Engineering March 2016 Topics 1 General structure 2 General properties 3 Cell layout João Canas Ferreira (FEUP) CMOS logic gates March
More informationDigital Integrated Circuits 2nd Inverter
Digital Integrated Circuits The Inverter The CMOS Inverter V DD Analysis Inverter complex gate Cost V in V out complexity & Area Integrity and robustness C L Static behavior Performance Dynamic response
More informationDKDT: A Performance Aware Dual Dielectric Assignment for Tunneling Current Reduction
DKDT: A Performance Aware Dual Dielectric Assignment for Tunneling Current Reduction Saraju P. Mohanty Dept of Computer Science and Engineering University of North Texas smohanty@cs.unt.edu http://www.cs.unt.edu/~smohanty/
More information