5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1


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1 5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1
2 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design 2
3 CMOS Inverter p+ p+ n+ n+ p n n+ V IN V SS V OUT V DD W.Kucewicz VLSICirciuit Design 3
4 CMOS Inverter V DD V DD V OUT = 1 V OUT = 0 V IN = 0 V IN = V DD W.Kucewicz VLSICirciuit Design 4
5 CMOS Inverter Properties Full railto torail swing high noise margins Logic levels not dependent upon the relative device sizes ratioless Always a path to V DD or V SS (Gnd) in steady state low output impedance (output resistance in kωk range) Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steadystate state input current No direct path steadystate state between power and ground no static power dissipation Propagation delay function of load capacitance and resistance of transistors W.Kucewicz VLSICirciuit Design 5
6 CMOS Inverter NMOS transistor, 0.25µm, PMOS transistor, 0.25µm, L d = 0.25µm, W/L = 1.5, L d = 0.25µm, W/L = 1.5, DD = 2.5V, V T = 0.4V DD = 2.5V, V T = 0.4V V DD V DD W.Kucewicz VLSICirciuit Design 6
7 CMOS Inverter Relative Transistor Size When designing static CMOS circuits, balance the driving strengths of the transistors by making the PMOS section wider than the NMOS section to maximize the noise margins and obtain symmetrical characteristics W.Kucewicz VLSICirciuit Design 7
8 CMOS Inverter Want common coordinate set V in, V out, and I Dn W.Kucewicz VLSICirciuit Design 8
9 CMOS Inverter 0.25µm, W/L n = 1.5, W/L p = 4.5, V DD = 2.5V, V Tn = 0.4V, V Tp = 0.4V W.Kucewicz VLSICirciuit Design 9
10 CMOS Inverter W.Kucewicz VLSICirciuit Design 10
11 Switching Threshold V M W.Kucewicz VLSICirciuit Design 11
12 Switching Threshold Example W.Kucewicz VLSICirciuit Design 12
13 Simulated Switching Threshold V M (V) V M is relatively insensitive to variations in device ratio. Setting the ratio to 3, 2.5, and 2 yields switching thresholds of 1.22 V, 1.18 V, and 1.13 V, respectively. 2 3 W p /W n Increasing the width of the PMOS moves V M towards V DD Increasing the width of the NMOS moves V M toward GND Simulated inverter switching threshold versus PMOS/NMOS ratio (0.25 µm CMOS, V DD = 2.5 V) W.Kucewicz VLSICirciuit Design 13
14 Noise Margins V OH = V DD V Out V M V OL = GND V IL V IH V IN W.Kucewicz VLSICirciuit Design 14
15 Gain V IL V IH W.Kucewicz VLSICirciuit Design 15
16 Impact of Process Variation on VTC Curve V Out V M V In Process variations (mostly) cause a shift in the switching threshold hold W.Kucewicz VLSICirciuit Design 16
17 Scaling the Supply Voltage V Out g ~ 1/V V M M ~ V DD Device threshold voltages are kept (virtually) constant V In Why do not operate with low V DD? DC characteristics became sensitive to variation of parameters such as V T more sensitive to the external noise (not scalable) W.Kucewicz VLSICirciuit Design 17
18 Dynamic Behaviour V DD V DD V OUT V OUT V IN = 0 V IN = V DD W.Kucewicz VLSICirciuit Design 18
19 Dynamic Behaviour V DD V DD V OUT V OUT V IN = 0 V IN = V DD Gate response time is determined by the time to charge C L through R p (discharge C L through R n ) W.Kucewicz VLSICirciuit Design 19
20 MOS Inverter Dynamic Behaviour W.Kucewicz VLSICirciuit Design 20
21 Capacitance Sources wiring capacitance intrinsic MOS transistor capacitances extrinsic MOS transistor capacitances W.Kucewicz VLSICirciuit Design 21
22 The Miller Effect A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground whose value is two times the original value W.Kucewicz VLSICirciuit Design 22
23 Layout W.Kucewicz VLSICirciuit Design 23
24 Capacitance Calculations where C 0 overlap capacitance C j bottom junction capacitance C jsw side wall junction capacitance Cox gate capacitance Keq linearization factor of bottom junction capacitance (C = k eq *C j ) eqsw linearization factor of side wall junction capacitance K eqsw W.Kucewicz VLSICirciuit Design 24
25 Capacitance Calculations W.Kucewicz VLSICirciuit Design 25
26 Inverter Propagation Delay W.Kucewicz VLSICirciuit Design 26
27 Inverter Transient Respons t phl t plh phl = 36 ps plh = 29 ps W.Kucewicz VLSICirciuit Design 27
28 Inverter Propagation Dealy W.Kucewicz VLSICirciuit Design 28
29 Design for Performance Reduce C L internal diffusion capacitance of the gate itself interconnect capacitance fanout Increase W/L ratio of the transistor the most powerful and effective performance optimization tool in the hands of the designer watch out for selfloading loading! Increase V DD only minimal improvement in performance at the cost of increased energy dissipation W.Kucewicz VLSICirciuit Design 29
30 Device Sizing for Performance Divide capacitive load into intrinsic  diffusion and Miller effect extrinsic  wiring and fanout C L = C int + C ext = C int (1 + α) Widening both PMOS and NMOS by a factor S reduces R eq by an identical factor, but raises the intrinsic capacitance by the same factor t p = (1 + α/s) /S)t p0 where t p0 is the intrinsic delay of the gate (α( = 0) W.Kucewicz VLSICirciuit Design 30
31 Sizing Impacts on Delay Any sizing factor that is sufficiently larger than α will give only minimal performance W.Kucewicz VLSICirciuit Design 31
32 Impact of Fanout Extrinsic capacitance is a function of the fanout of the gate  the larger the fanout,, the larger the external load. With fanout N Linear dependence t p (N) = t p0 (1 + αn) avoid large fanout if performance is an issue Increasing the sizing factor S of the driving inverter is recommended for larger fanout W.Kucewicz VLSICirciuit Design 32
33 NMOS/PMOS Ratio So far have sized the PMOS and NMOS so that the R eq s match (ratio of 3 to 3.5) symmetrical VTC equal highto tolow and lowto tohigh propagation delays If speed is the only concern, reduce the width of the PMOS device! widening the PMOS degrades the t phl due to larger parasitic capacitance β = (W/L p )/(W/L n ) r = R eqp /R eqn (resistance ratio of identicallysized PMOS and NMOS) β opt = r (~2) when wiring capacitance is negligible W.Kucewicz VLSICirciuit Design 33
34 NMOS/PMOS Ratio Effects β of 2.4 gives symmetrical response β of 1.6 to 1.9 gives optimal performance W.Kucewicz VLSICirciuit Design 34
35 Input Signal Rise/Fall Time In reality, the input signal changes gradually (and both PMOS and NMOS conduct for a brief time). This affects the current available for charging /discharging C L and impacts propagation delay. t p increases linearly with increasing input slope once t p as a function of input signal slope t s for a minimumsize inverter with a fan out of a single gate t s > t p W.Kucewicz VLSICirciuit Design 35
36 Design Challenge Keep signal rise times smaller than or equal to the gate propagation delays. good for performance good for power consumption Keeping rise and fall times of the signals small and of approximately equal values is one of the major challenges in highperformance designs W.Kucewicz VLSICirciuit Design 36
37 Delay with Long Interconnections When gates are farther apart, wire capacitance and resistance can no longer be ignored. W.Kucewicz VLSICirciuit Design 37
38 Dynamic Power Consumpsion P dyn P dyn = C L V 2 DD f P dyn = 6pF 2.5V 500MHz = 50µW 1M gates P tot = 50W P tot W.Kucewicz VLSICirciuit Design 38
39 DirectPath Currents Power Consumpsion P d = t s I Peak V DD f P dyn dyn = 100ps 200 µa 2.5V 500MHz = 2.5 µw 1M gates P tot = 2.5 W W.Kucewicz VLSICirciuit Design 39
40 Static Power Consumpsion P stat P stat = I stat V DD P stat stat = 10pA/µm µm 2 2.5V = 125 pw 1M gates P tot = 125 µw W.Kucewicz VLSICirciuit Design 40
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