# Integrated Circuits & Systems

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1 Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 13 The CMOS Inverter: dynamic behavior (delay)

2 Abstractions Electric-level Electrical Schematics Logic-level Logic Schematics in out V in V out Truth Table in out Slide 13.2

3 Dynamic Behavior R p in out V in = 0V V out = C L V in = V out = 0V C L R n R n and R p are the on-resistance (Ro n ) of NMOS, PMOS, respect. C L represents the total charge attached to the gate s output Slide 13.3

4 Dynamic Behavior Steady State Vin V in = 0V R p V out = Vout 0V t C L 0V t Falling Transition Vin Vin= (0 ) R p i Vout = ( 0) Vout 0V t R n C L 0V t Steady State Vin V in = V out = 0V Vout 0V t R n C L 0V t Slide 13.4

5 Dynamic Behavior Steady State Vin V in = V out = 0V Vout 0V t R n C L 0V t Rising Transition Vin 0V t Vin= ( 0) R p R n i Vout = (0 ) C L Vout 0V t Steady State Vin V in = 0V R p V out = Vout 0V t C L 0V t Slide 13.5

6 Delay Definitions Propagation delay (V in x V out ): V in t phl = propagation delay for (output) fall transition 50% t plh = propagation delay for (output) rise transition V out t phl 50% t plh 90% t Fall and Rise Times: t f = fall time t r = rise time 10% t f t r t Adapted from: Rabaey; Chandrakasan; Nikolic, 2003 Slide 13.6

7 Propagation Delay: First-Order Analysis How to Compute? t p = v 2 v 1 C L(v) i(v) dv With i the (dis)charging current v, the voltage over the capacitor, v 1 and v 2 are the initial and final voltages, respectively. Intractable: i(v) and C L (v) are non-linear functions of v! For manual analysis, we would rather rely on a simplified switch model! Slide 13.7

8 Propagation Delay: First-Order Analysis Using a constant value for R on we fall into the case of an RC network, where R=R eq and C=C L R eq = 1 /2 /2 V dv 3 I DSAT (1+ λv ) 4I DSAT λv DD with W I DSAT = k' L (V DD V T )V DSAT V 2 DSAT 2 V out C L t phl = ln(2) R eq. C L = 0.69 R n. C L R n Slide 13.8

9 Propagation Delay: First-Order Analysis t phl = f (R n.c L ) = t = f (R plh p.c L ) = R n.c R p.c L L R p V out V out C L C L R n Sometimes, an average propagation delay value may be useful: t p = t plh + t phl 2 Slide 13.9

10 How to Get a Faster Inverter? 1. Keeping C L Small (Fanout, routing and self-loading ) t phl = f (R n.c L ) = t = f (R plh p.c L ) = R n.c R p.c L L R p V out V out C L C L R n Slide 13.10

11 How to Get a Faster Inverter? 2. Decreasing the on-resistance of transistors R, I L=Lmin ~R/2, ~2xI L=Lmin Watch out for self-loading! 2W W In digital design, W is usually kept minimum Slide 13.11

12 Computing Capacitances Lumping All Capacitances into C L at Inv1 s Output Node Inv1 Inv2 Assuming an ideal voltage source with zero fall and rise times M2 M4 V in C gd12 C db2 V out C g4 V out2 M1 C db1 C w C g3 M3 Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 13.12

13 Computing Capacitances Gate-Drain Capacitance C gd12 Inv1 Inv2 Overlap capacitances of M1 and M2 M2 M4 V in C gd12 C db2 V out C g4 V out2 But we have to use a grounded equivalent value for C gd12 M1 C db1 C w C g3 M3 Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 13.13

14 Computing Capacitances Gate-Drain Capacitance C gd12 Taking the Miller Effect into account ΔV V in C gd12 V out ΔV V out ΔV M1 ΔV V in M1 2C gd12 For each transistor: C gd = 2 C GD0 W Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 13.14

15 Computing Capacitances Diffusion Capacitances C db1 and C db2 Due to the reverse biased p-n junctions Inv1 Inv2 Quite non-linear M2 M4 V in C gd12 C db2 V out C g4 V out2 M1 C db1 C w C g3 M3 Slide 13.15

16 Computing Capacitances Diffusion Capacitances C db1 and C db2 Using K eq (from diode s theory) to linearize C db C eq = K eq C j0 K eq = φ 0 m (V high V low )(1 m) [(φ 0 V high )1 m (φ 0 Vlow) 1 m ] Slide 13.16

17 Computing Capacitances Diffusion Capacitances C db1 and C db2 K eq for a 0.25 µm inverter: K eq = C ox (ff/μm 2 ) Relevant capacitances for 0.25 µm transistors CGD0 (ff/μm) CJ (ff/μm 2 ) φ 0 m (V high V low )(1 m) [(φ 0 V high ) 1 m (φ 0 Vlow) 1 m ] m j ϕ b (V) CJSW (ff/μm) m jsw ϕ bsw (V) NMOS PMOS fall rise NMOS V low = 1.25V; V high = 2.5V K eq (m=0.5, ϕ 0 =0.9)= 0.57 K eqsw (m=0.44, ϕ 0 =0.9)= 0.61 V low = 0V; V high = 1.25V K eq (m=0.5, ϕ 0 =0.9)= 0.79 K eqsw (m=0.44, ϕ 0 =0.9)= 0.81 PMOS V low =0V; V high = 1.25V K eq (m=0.48, ϕ 0 =0.9)= 0.79 K eqsw (m=0.32, ϕ 0 =0.9)= 0.86 V low = 1.25V; V high = 2.5V K eq (m=0.48, ϕ 0 =0.9)= 0.59 K eqsw (m=0.32, ϕ 0 =0.9)= 0.7 Slide 13.17

18 Computing Capacitances Wiring Capacitances C w Inv1 Inv2 M2 M4 V in C gd12 C db2 V out C g4 V out2 M1 C db1 C w C g3 M3 Slide 13.18

19 Computing Capacitances Gate Capacitance of Fanout C g3 and C g4 Inv1 Inv2 M2 M4 V in C gd12 C db2 V out C g4 V out2 M1 C db1 C w C g3 M3 C fanout = C gate (NMOS ) + C gate (PMOS) = (C GS0n + C GD0n + W n L n C ox ) + (C GS0p + C GD0p + W p L p C ox ) Ignores the Miller Effect Assumes C gate is constant Slide 13.19

20 Computing Capacitances Inverter in 0.25µm CMOS technology W n /L n = 0.375µm/0.25µm (9λ/2λ) W p /L p = 1.125µm/0.25µm NMOS: PD = ( ) x λ = 15 x λ = 15 x 0.125µm = 1.875µm AD = (4 x 4) λ 2 + (3 x 1) λ 2 = 19λ 2 = 0.30 µm µm = 2λ (3λ/2λ) Slide Source: Rabaey; Chandrakasan; Nikolic, 2003

21 Computing Capacitances Inverter in 0.25µm CMOS technology W n /L n = 0.375µm/0.25µm (9λ/2λ) W p /L p = 1.125µm/0.25µm PMOS: PD = (5+9+5) x λ = 19 x λ = 19 x 0.125µm = 2.375µm AD = (5 x 9) λ 2 = 45λ 2 = 0.70 µm µm = 2λ (3λ/2λ) Slide Source: Rabaey; Chandrakasan; Nikolic, 2003

22 Computing Capacitances W/L AD(μm 2 ) PD(μm) AS(μm 2 ) PS(μm) NMOS 0.375/ (19λ 2 ) (15λ) 0.3 (19λ 2 ) (15λ) PMOS 1.125/ (45λ 2 ) (19λ) 0.7 (45λ 2 ) (19λ) C ox (ff/μm 2 ) Relevant capacitances for 0.25 µm transistors CGD0 (ff/μm) CJ (ff/μm 2 ) m j ϕ b (V) CJSW (ff/μm) m jsw ϕ bsw (V) NMOS PMOS Slide 13.22

23 Computing Capacitances capacitor capacitor Value (ff) (H L) Value (ff) (L H) C gd1 2 CGD0 n W n C gd2 2 CGD0 p W p C db1 K eqn AD n CJ + K eqswn PD n CJSW C db2 K eqp AD p CJ + K eqswp PD p CJSW C g3 (CGD0 n + CGS0 n ) W n + W n L n C ox C g4 (CGD0 p + CGS0 p ) W p + W p L p C ox Cw Provided by extraction tool C L Σ Slide 13.23

24 Propagation Delay of an Inverter Example Compute the propagation delays for the inverter of previous slides. From the layout, W n /L n = 1.5 and W p /L p = 4.5 (assuming that W W d and L L d ). From lecture 11, Normalized R eq of NMOS and PMOS Transistors in 0.25 µm (W/L=1, L=L min ) (V) NMOS (kω) PMOS (kω t phl = kΩ 6.1fF = 36ps 1.5 t plh = kΩ 6.0 ff = 29ps 4.5 Slide 13.24

25 Propagation Delay of an Inverter Spice Simulation Results t phl = 39.9 ps t plh = 31.7 ps Good accuracy? (a stroke of good luck ) Overshooting: gate-drain capacitances couple output to input Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 13.25

26 Spice Simulations for the Inverter Simulation Circuit M2 in out M1 C L C L represents the output load seen by this inverter (assuming the lumped model) Slide 13.26

27 Spice Simulations for the Inverter File inversor-v0.cir ( ) * Simulacao de um inversor CMOS * Inclusao de arquivo de tecnologia.include parametros.txt * Fonte de alimentacao V1 vdd 0 dc 3.3 V2 gnd 0 dc 0 * Fonte de tensao que serve de estimulo para a entrada V3 in 0 pulse( n 200p 200p 2n 4n) *Descricao de um inversor com trans. minimos em tecnologia 0.35um *Entrada= "in"; saida="out" M2 vdd in out vdd PMOS l=0.35u w=0.4u pd=1.4u ad=0.2p ps=1.4u as=0.2p M1 gnd in out gnd NMOS l=0.35u w=0.4u pd=1.4u ad=0.2p ps=1.4u as=0.2p * Capacitancia para representar carga vista pela saida da porta CL out 0 20f.control.endc.end tran 0.1p 6n plot in out Slide 13.27

28 Spice Simulations for the Inverter File inversor-v0.cir ( ) * Simulacao de um inversor CMOS * Inclusao de arquivo de tecnologia.include parametros.txt * Fonte de alimentacao V1 vdd 0 dc 3.3 V2 gnd 0 dc 0 Specific of SpiceOpus. Allows for using the node names vdd and gnd instead of 0 and 1. * Fonte de tensao que serve de estimulo para a entrada V3 in 0 pulse( n 200p 200p 2n 4n) *Descricao de um inversor com trans. minimos em tecnologia 0.35um *Entrada= "in"; saida="out" M2 vdd in out vdd PMOS l=0.35u w=0.4u pd=1.4u ad=0.2p ps=1.4u as=0.2p M1 gnd in out gnd NMOS l=0.35u w=0.4u pd=1.4u ad=0.2p ps=1.4u as=0.2p * Capacitancia para representar carga vista pela saida da porta CL out 0 20f.control.endc.end tran 0.1p 6n plot in out Slide 13.28

29 Spice Simulations for the Inverter File inversor-v0.cir ( ) * Simulacao de um inversor CMOS * Inclusao de arquivo de tecnologia.include parametros.txt * Fonte de alimentacao V1 vdd 0 dc 3.3 V2 gnd 0 dc 0 * Fonte de tensao que serve de estimulo para a entrada V3 in 0 pulse( n 200p 200p 2n 4n) 2ns (=delay) 4ns (=period) V1=3.3V 2ns (=tv2) V2=0V 200ps (time v1 to v2) 200ps (time v2 to v1) Rise and fall times Slide 13.29

30 Spice Simulations for the Inverter File inversor-v0.cir ( ) *Descricao de um inversor com trans. minimos em tecnologia 0.35um *Entrada= "in"; saida="out" M2 vdd in out vdd PMOS l=0.35u w=0.4u pd=1.4u ad=0.2p ps=1.4u as=0.2p M1 gnd in out gnd NMOS l=0.35u w=0.4u pd=1.4u ad=0.2p ps=1.4u as=0.2p pd = drain perimeter [m] ad = drain area [m 2 ] ps = source perimeter [m] as = source area [m 2 ] Where do such dimensions come from? Let us assume the minimal dimensions of an actual 0.35µm technology Slide 13.30

31 Spice Simulations for the Inverter File inversor-v0.cir ( ) *Descricao de um inversor com trans. minimos em tecnologia 0.35um *Entrada= "in"; saida="out" M2 vdd in out vdd PMOS l=0.35u w=0.4u pd=1.4u ad=0.2p ps=1.4u as=0.2p M1 gnd in out gnd NMOS l=0.35u w=0.4u pd=1.4u ad=0.2p ps=1.4u as=0.2p two serial transistors with minimal dimensions in 0.35µm technology L min = 0.35µm 0,4µm 0,4µm 0,5µm 0,45µm L min NMOS = L min PMOS = 0.35µm W min NMOS = W min PMOS = 0.4µm Minimum width of poly for connection = 0,35µm Slide 13.31

32 Spice Simulations for the Inverter File inversor-v0.cir ( ) * Simulacao de um inversor CMOS * Inclusao de arquivo de tecnologia.include parametros.txt * Fonte de alimentacao V1 vdd 0 dc 3.3 V2 gnd 0 dc 0 * Fonte de tensao que serve de estimulo para a entrada V3 in 0 pulse( n 200p 200p 2n 4n) *Descricao de um inversor com trans. minimos em tecnologia 0.35um *Entrada= "in"; saida="out" M2 vdd in out vdd PMOS l=0.35u w=0.4u pd=1.4u ad=0.2p ps=1.4u as=0.2p M1 gnd in out gnd NMOS l=0.35u w=0.4u pd=1.4u ad=0.2p ps=1.4u as=0.2p * Capacitancia para representar carga vista pela saida da porta CL out 0 20f.control.endc.end tran 0.1p 6n plot in out Capacitance to represent the output load seen by this inverter (~= to another gate in the same technology) Slide 13.32

33 Spice Simulations for the Inverter File inversor-v0.cir ( ) *Descricao de um inversor com trans. minimos em tecnologia 0.35um *Entrada= "in"; saida="out" M2 vdd in out vdd PMOS l=0.35u w=0.4u pd=1.4u ad=0.2p ps=1.4u as=0.2p M1 gnd in out gnd NMOS l=0.35u w=0.4u pd=1.4u ad=0.2p ps=1.4u as=0.2p * Capacitancia para representar carga vista pela saida da porta CL out 0 20f.control.endc.end tran 0.1p 6n plot in out Simulation step Total simulation time Print commands (within a segment.control..endc ) This is specific from SpiceOpus Slide 13.33

34 Spice Simulations for the Inverter Simulation Waveforms in tp LH out tp HL t plh =458ps t phl =180ps Slide 13.34

35 (Nearly) Actual Layout The CMOS Inverter Two transistors in series with one contact (assuming typical 0.35 µm CMOS Design Rules) L min = 0.35µm L min = 0.35µm 0,4µm 0,4µm b 0,45µm 0,5µm 0,4µm 0,45µm a 0,4µm 0,4µm b a=0,3µm (minimum diffusion contact to gate spacing) b=0,15µm (minimum diffusion enclosure to contact) Slide 13.35

36 (Nearly) Actual Layout The CMOS Inverter Two transistors in series with wider chanels (asuming typical 0.35 µm CMOS Design Rules) L min = 0.35µm L min = 0.35µm 0,4µm b 0,4µm 0,4µm b 0,4µm 0,4µm b 0,4µm 0,45µm a 0,4µm 0,45µm a 0,4µm b a=0,3µm (minimum diffusion contact to gate spacing) b=0,15µm (minimum diffusion enclosure to contact) minimum contact spacing =0,4µm Slide 13.36

37 (Nearly) Actual Layout The CMOS Inverter Inverter in a typical 0.35 µm CMOS technology a=0,3µm (minimum diffusion contact to gate spacing) b=0,15µm (minimum diffusion enclosure to contact) Obs: min. width of metal lines = 0,7µm PMOS: W=W min =0.35µm L=1.5 µm Slide in NMOS: W=W min =0.35µm L=0.7 µm 0,4µm b 0,4µm 0,4µm 0,4µm 0,4µm Vdd b b b out Gnd

38 Spice Simulations for the Inverter - 2 File inversor-v1.cir ( ) * Simulacao de um inversor CMOS * Inclusao de arquivo de tecnologia.include parametros.txt * Fonte de alimentacao V1 vdd 0 dc 3.3 V2 gnd 0 dc 0 * Fonte de tensao que serve de estimulo para a entrada V3 in 0 pulse( n 200p 200p 2n 4n) *Descricao de um inversor com trans. minimos em tecnologia 0.35um *Entrada= "in"; saida="out" M2 vdd in out vdd PMOS l=0.35u w=1.5u pd=3.2u ad=1.275p ps=3.2u as=1.275p M1 gnd in out gnd NMOS l=0.35u w=0.7u pd=2.4u ad=0.595p ps=2.4u as=0.595p * Capacitancia para representar carga vista pela saida da porta CL out 0 20f.control.endc.end tran 0.1p 6n plot in out Slide 13.38

39 Spice Simulations for the Inverter - 2 Simulation Waveforms in tp LH out tp HL t plh =170ps t phl =151ps Slide 13.39

40 Delay as Function of Very sensitive do Similar in shape to the R eq x curve Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 13.40

41 To Minimize Propagation Delay of a Gate Reduce C L Keep the drain diffusion areas as small as possible (to reduce selfloading capacitance) Place fanout gates as close as possible (to reduce routing capacitance) Increase the W/L ratio of the transistors Most powerful and effective design action Caution: it increases diffusion capacitance (and thus, C L ) It also increases gate capacitances (thus increasing the fanout factor of the driving gate) Increase Above certain levels yields only minimal improvements Increases power consumption and dissipation Slide 13.41

42 The References CMOS Inverter 1. RABAEY, J; CHANDRAKASAN, A.; NIKOLIC, B. Digital Integrated Circuits: a design perspective. 2 nd Edition. Prentice Hall, ISBN: WESTE, Neil; HARRIS, David. CMOS VLSI Design: a circuits and systems perspective. Addison-Wesley, 4 th Edition, ISBN Slide 13.42

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