CPE/EE 427, CPE 527 VLSI Design I Pass Transistor Logic. Review: CMOS Circuit Styles


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1 PE/EE 427, PE 527 VLI Design I Pass Transistor Logic Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( ) Review: MO ircuit tyles tatic complementary MO  except during switching, output connected to either VDD or GND via a lowresistance path high noise margins full rail to rail swing VOH and VOL are at VDD and GND, respectively low output impedance, high input impedance no steady state path between VDD and GND (no static power consumption) delay a function of load capacitance and transistor resistance comparable rise and fall times (under the appropriate transistor sizing conditions) Dynamic MO  relies on temporary storage of signal values on the capacitance of highimpedance circuit nodes simpler, faster gates increased sensitivity to noise 9/18/26 VLI Design I;. Milenkovic 2 VLI Design I;. Milenkovic 1
2 Review: tatic omplementary MO Pullup network (PUN) and pulldown network (PDN) In 1 In 2 In N In 1 In 2 In N V DD PUN PDN PMO transistors only pullup: make a connection from V DD to F when F(In 1,In 2, In N ) = 1 F(In 1,In 2, In N ) pulldown: make a connection from F to GND when F(In 1,In 2, In N ) = NMO transistors only PUN and PDN are dual logic networks 9/18/26 VLI Design I;. Milenkovic 3 OI221 Vdd D E D E Z GND 9/18/26 VLI Design I;. Milenkovic 4 VLI Design I;. Milenkovic 2
3 Pass Transistor Logic NMO Transistors in eries/parallel Primary inputs drive both gate and source/drain terminals NMO switch closes when the gate input is high X Y X = Y if and X Y X = Y if or Remember NMO transistors pass a strong but a weak 1 9/18/26 VLI Design I;. Milenkovic 6 VLI Design I;. Milenkovic 3
4 PMO Transistors in eries/parallel Primary inputs drive both gate and source/drain terminals PMO switch closes when the gate input is low X Y X = Y if and = + X Y X = Y if or = Remember PMO transistors pass a strong 1 but a weak 9/18/26 VLI Design I;. Milenkovic 7 Pass Transistor (PT) Logic F = F = Gate is static a lowimpedance path exists to both supply rails under all circumstances N transistors instead of 2N No static power consumption Ratioless idirectional (versus undirectional) 9/18/26 VLI Design I;. Milenkovic 8 VLI Design I;. Milenkovic 4
5 VT of PT ND Gate 1.5/ /.25.5/.25.5/.25 F= V out, V 1 =V DD, = V DD =V DD, = V DD == V DD 1 2 V in, V Pure PT logic is not regenerative  the signal gradually degrades after passing through a number of PTs (can fix with static MO inverter insertion) 9/18/26 VLI Design I;. Milenkovic 9 Differential PT Logic (PL) PT Network F F Inverse PT Network F F F= F=+ F= ND/NND F= OR/NOR F=+ XOR/XNOR F= 9/18/26 VLI Design I;. Milenkovic 1 VLI Design I;. Milenkovic 5
6 PL Properties Differential so complementary data inputs and outputs are always available (so don t need extra inverters) till static, since the output defining nodes are always tied to V DD or GND through a low resistance path Design is modular; all gates use the same topology, only the inputs are permuted. imple XOR makes it attractive for structures like adders Fast (assuming number of transistors in series is small) dditional routing overhead for complementary signals till have static power dissipation problems 9/18/26 VLI Design I;. Milenkovic 11 PL Full dder!um um! out out 9/18/26 VLI Design I;. Milenkovic 12 VLI Design I;. Milenkovic 6
7 PL Full dder!um um! out out 9/18/26 VLI Design I;. Milenkovic 13 NMO Only PT Driving an Inverter In = V DD V x = V G = V V DD DD V Tn D M 1 M 2 V x does not pull up to V DD, but V DD V Tn Threshold voltage drop causes static power consumption (M 2 may be weakly conducting forming a path from V DD to GND) Notice V Tn increases of pass transistor due to body effect (V ) 9/18/26 VLI Design I;. Milenkovic 14 VLI Design I;. Milenkovic 7
8 Voltage wing of PT Driving an Inverter V DD In = V DD D.5/.25 x 1.5/.25.5/.25 Out Voltage, V Out In x = 1.8V Time, ns ody effect large V at x  when pulling high ( is tied to GND and charged up close to V DD ) o the voltage drop is even worse V x = V DD (V Tn + γ( ( 2φ f + V x )  2φ f )) 9/18/26 VLI Design I;. Milenkovic 15 ascaded NMO Only PTs = V DD = V DD G M 1 = V DD x = V DD V Tn1 G y M 2 = V DD Out = V DD = V DD M 1 x M 2 y Out wing on y = V DD V Tn1 V Tn2 wing on y = V DD V Tn1 Pass transistor gates should never be cascaded as on the left Logic on the right suffers from static power dissipation and reduced noise margins 9/18/26 VLI Design I;. Milenkovic 16 VLI Design I;. Milenkovic 8
9 olution 1: Level Restorer Level Restorer =1 M 2 Out= = M n M r x= 1 For correct operation M r must be sized correctly (ratioed) on off M 1 Out =1 Full swing on x (due to Level Restorer) so no static power consumption by inverter No static backward current path through Level Restorer and PT since Restorer is only active when is high 9/18/26 VLI Design I;. Milenkovic 17 Transient Level Restorer ircuit Response 3 W/L 2 =1.5/.25 W/L n =.5/.25 W/L 1 =.5/.25 Voltage, V 2 1 W/L r =1.75/.25 W/L r =1.5/.25 node x never goes below V M of inverter so output never switches W/L r =1./.25 W/L r =1.25/ Time, ps Restorer has speed and power impacts: increases the capacitance at x, slowing down the gate; increases t r (but decreases t f ) 9/18/26 VLI Design I;. Milenkovic 18 VLI Design I;. Milenkovic 9
10 olution 2: Multiple V T Transistors Technology solution: Use (near) zero V T devices for the NMO PTs to eliminate most of the threshold drop (body effect still in force preventing full swing to V DD ) low V T transistors In 2 = V = 2.5V on Out In 1 = 2.5V off but leaking = V sneak path Impacts static power consumption due to subthreshold currents flowing through the PTs (even if V G is below V T ) 9/18/26 VLI Design I;. Milenkovic 19 olution 3: Transmission Gates (TGs) Most widely used solution = GND = GND = V DD = GND = V DD = V DD Full swing bidirectional switch controlled by the gate signal, = if = 1 9/18/26 VLI Design I;. Milenkovic 2 VLI Design I;. Milenkovic 1
11 olution 3: Transmission Gates (TGs) Most widely used solution = GND = GND = V DD = GND = V DD = V DD Full swing bidirectional switch controlled by the gate signal, = if = 1 9/18/26 VLI Design I;. Milenkovic 21 Resistance of TG 3 25 R n W/L p =.5/.25 V R p Resistance, kω R p 2.5V V out R n 2.5V R eq W/L n =.5/ V out, V 9/18/26 VLI Design I;. Milenkovic 22 VLI Design I;. Milenkovic 11
12 TG Multiplexer F V DD In 2 F In 1 F =!(In 1 + In 2 ) GND In 1 In 2 9/18/26 VLI Design I;. Milenkovic 23 Transmission Gate XOR 9/18/26 VLI Design I;. Milenkovic 24 VLI Design I;. Milenkovic 12
13 Transmission Gate XOR weak if! 1 on off on off!! weak 1 if an inverter 9/18/26 VLI Design I;. Milenkovic 25 TG Full dder um out 9/18/26 VLI Design I;. Milenkovic 26 VLI Design I;. Milenkovic 13
14 Differential TG Logic (DPL) GND F= F= GND V DD F= F= V DD ND/NND XOR/XNOR 9/18/26 VLI Design I;. Milenkovic 27 VLI Design I;. Milenkovic 14
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