Properties of CMOS Gates Snapshot


 Rosalyn Hutchinson
 5 years ago
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1 MOS logic 1
2 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND) in steadystate mode. omparable rise and fall times: (under appropriate sizing conditions) Extremely high input resistance: nearly zero steadystate input current. lways a path to Vdd or Gnd in steady state: low output impedance. 2
3 Static MOS ircuit  t every point in time (except during the switching transients) each gate output is connected to either V DD or V ss via a lowresistive path.  The outputs of the gates assume at all times the value of the oolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods).  This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. 3
4 Static omplementary MOS V DD In1 In2 InN In1 In2 InN PUN PDN PMOS only NMOS only F(In1,In2, InN) PUN and PDN are dual logic networks 4
5 Threshold Drops PUN V DD V DD S D V DD D 0 V DD V GS S 0 V DD V Tn L L PDN V DD 0 V DD V Tp V DD D L V GS S L S D 5
6 NMOS Transistors in Series/Parallel onnection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high X Y Y = X if and X Y Y = X if OR NMOS Transistors pass a strong 0 but a weak 1 6
7 PMOS Transistors in Series/Parallel onnection PMOS switch closes when switch control input is low X Y Y = X if ND = + X Y Y = X if OR = PMOS Transistors pass a strong 1 but a weak 0 7
8 omplementary MOS Logic Style 8
9 Example Gate: NND 9
10 Example Gate: NOR 10
11 Twoinput MOS NOR gate and reference inverter 11
12 MOS NOR Gate Truth Table and Transistor States 12
13 Threeinput MOS NOR gate and reference inverter 13
14 Twoinput MOS NND gate and reference inverter 14
15 Switch Delay Model R eq R p R p R p R p R n L R n L R p int NND2 R n int INV R n R n L NOR2 15
16 Input Pattern Effects on Delay R p R n R n R p L int Delay is dependent on the pattern of inputs Low to high transition both inputs go low delay is 0.69 R p /2 L one input goes low delay is 0.69 R p L High to low transition both inputs go high delay is R n L 16
17 Delay Dependence on Input Patterns Voltage [V] 3 2,5 2 1,5 1 0,5 00,5 ==1 0 =1, =1 0 =1 0, = time [ps] Input Data Pattern ==0 1 =1, =0 1 = 0 1, =1 ==1 0 =1, =1 0 = 1 0, =1 Delay (psec) NMOS = 0.5μm/0.25 μm PMOS = 0.75μm/0.25 μm L = 100 ff
18 FanIn onsiderations D M4 M3 3 L Distributed R model (Elmore delay) D M2 M1 2 1 t phl = 0.69 R eqn ( L ) Propagation delay deteriorates rapidly as a function of fanin quadratically in the worst case. 18
19 t p of MOS NND as a function of FanIn t p (psec) t phl fanin t p t plh quadratic linear Gates with a fanin greater than 4 should be avoided. 19
20 t p as a Function of FanOut t p (psec) t p NOR2 t p NND2 t p INV eff. fanout ll gates have the same drive current. Slope is a function of driving strength 20
21 t p as a Function of FanIn and Fan Out Fanin: quadratic due to increasing resistance and capacitance Fanout: each additional fanout gate adds two gate capacitances to L t p = a 1 FI + a 2 FI 2 + a 3 FO 21
22 Design Techniques for large fanin Transistor sizing as long as fanout capacitance dominates Progressive sizing In N MN L Distributed R line M1 > M2 > M3 > > MN (the fet closest to the output is the smallest) In 3 M3 3 In 2 In 1 M2 M1 2 1 an reduce delay by more than 20%; decreasing gains as technology shrinks 22
23 Transistor ordering critical path critical path In 3 1 M3 charged L 0 1 In 1 M3 L charged In 2 1 M2 2 charged In 2 1 M2 2 discharged In M1 1 charged In 3 1 M1 1 discharged delay determined by time to discharge L, 1 and 2 delay determined by time to discharge L 23
24 lternative logic structures F = DEFGH 24
25 Isolating fanin from fanout using buffer insertion L L 25
26 Power consumption in MOS logic gates 26
27 X Z X Z Example illustrating the effect of signal correlations 27
28 Glitching in Static MOS 28
29 Example: hain of NND Gates 29
30 How to ope with Glitching? D D,,, 30
31 Input ordering X Z P(=1) = 0.5 P(=1) = 0.2 Y Z P(=1) = 0.1 Reordering of inputs affects the circuit activity 31
32 Time multiplexing resources 32
33 Ratioed Logic V DD V DD V DD Resistive Load R L Depletion Load V T < 0 PMOS Load F F V SS F In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN V SS V SS V SS (a) resistive load (b) depletion load NMOS (c) pseudonmos Goal: to reduce the number of devices over complementary MOS 33
34 Resistive Load V DD Resistive Load R L N transistors + Load V OH = V DD F V OL = R PN R PN + R L In 1 In 2 In 3 PDN ssymetrical response Static power consumption V SS t pl = 0.69 R L L 34
35 ctive Loads V DD V DD Depletion Load V T < 0 PMOS Load F V SS F In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN V SS V SS depletion load NMOS pseudonmos 35
36 PseudoNMOS Inverter VT W/L p = 4 V ou t [V] W/L p = W/L p = 0.5 W/L p = 0.25 W/L p = V in [V] 36
37 37
38 Fourinput pseudonmos NOR 38
39 Improved Loads V DD Enable M1 M2 M1 >> M2 F D L daptive Load 39
40 Improved Loads (2) V DD V DD M1 M2 Out Out PDN1 PDN2 V SS V SS Differential ascode Voltage Switch Logic (DVSL) 40
41 DVSL ND/NND Transient Response 2.5 V ol ta ge [V] ,, Time [ns] 41
42 PassTransistor Logic Inputs Switch Network Out Out N transistors No static consumption 42
43 Example: ND Gate F = 0 43
44 NMOSonly Switch = 2.5 V = 2.5 V = 2.5 V = 2.5 V X M 2 X M n L M 1 V does not pull up to 2.5V, but 2.5V V TN Threshold voltage loss causes static power consumption NMOS has higher threshold than PMOS (body effect) 44
45 NMOSOnly Only Logic V DD In x 0.5μm/0.25μm 1.5μm/ 0.25μm 0.5μm/ 0.25μm Out 3.0 In Voltage [V] Out x Time [ns] 45
46 Passtransistor output (drainsource) terminal should not drive other terminals to avoid multiple threshold drops 46
47 PassTransistor ND Gate VT 47
48 NMOS Only Logic: Level Restoring Transistor V DD Level Restorer V DD M r M 2 M n X Out M 1 dvantage: Full Swing Restorer adds capacitance, takes away pull down current at X Ratio problem 48
49 Restorer Sizing 3.0 W/L n = 0.5/0.25 V olta ge [V] W /L r =1.75/0.25 W /L r =1.50/0.25 W / L r =1.0/0.25 W /L r =1.25/ Time [ps] Upper limit on restorer size 49
50 Transmission Gate = 2.5 V = 2.5 V L = 0 V 50
51 Transmission Gate XOR M2 M1 F M3/M4 51
52 Resistance of Transmission Gate 30 R n 2. 5 V Rn Resistance, Kohms R p R n R p 2.5 V 0 V V ou t R p V ou t, V (W/L)p = (W/L)n = 0.5/
53 Delay in Transmission Gate Networks In V 1 V i1 V i V i+1 V n1 V n (a) In R eq R V eq R eq R 1 V i V i+1 V eq n1 V n m (b) R eq R eq R eq R eq R eq R eq In (c) 53
54 Delay Optimization 54
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