B.Supmonchai July 5th, q Quantification of Design Metrics of an inverter. q Optimization of an inverter design. B.Supmonchai Why CMOS Inverter?

Size: px
Start display at page:

Download "B.Supmonchai July 5th, q Quantification of Design Metrics of an inverter. q Optimization of an inverter design. B.Supmonchai Why CMOS Inverter?"

Transcription

1 July 5th, 4 Goals of This Chapter Quantification of Design Metrics of an inverter Static (or Steady-State) Behavior Chapter 5 CMOS Inverter Boonchuay Supmonchai Integrated Design Application Research (IDAR) Laboratory July 5, 4; Revised - June 5, 5 Dynamic (or Transient Response) Behavior Energy Efficiency Optimization of an inverter design Technology Scaling and its impact on the inverter metrics -545 Digital ICs CMOS Inverter Digital Gate Design Metrics: Recap Why CMOS Inverter? Cost Complexity and Area Reliability and Robustness Static Behavior Noise Margin, Regenerative Property Performance Dynamic Behavior Speed (Delay) Energy Efficiency Energy and Power Consumption, Energy-Delay CMOS because it is the dominating technology of the era. High Packing Density Relatively Easy Process Inverter because it is the nucleus of all digital designs. Behavior of more intricate structures (logic gates, adders, etc.) can be almost completely derived by extrapolating the results obtained from the inverters Digital ICs CMOS Inverter Digital ICs CMOS Inverter Digital ICs

2 July 5th, 4 CMOS Inverter: A First Glance CMOS Inverter: Physical View Recap Driven by Output Of another gate => Fanin PMOS In PMOS Out N Well PMOS l Contacts NMOS Collective Capacitances Of Wires and Gates => Fanout NMOS Polysilicon NMOS In Out Metal GND -545 Digital ICs CMOS Inverter Digital ICs CMOS Inverter 6 Two CMOS Inverters: Physical View CMOS Inverter Static Behavior Share power and ground R p Connect In Metal R n Vout Vout Abut Cells -545 Digital ICs CMOS Inverter 7 = = State of Transistors ON: V GT = V GS - V T > V T, R on Æ OFF: V GT = V GS - V T > V T, R off finite -545 Digital ICs CMOS Inverter Digital ICs

3 July 5th, 4 Charge Discharge R n Low to High High to Low = = response time is determined by the time to charge CL through lgate Rp (discharge through R n ) CMOS Inverter Dynamic Behavior R p CMOS Properties Full rail-to-rail swing High noise margins Logic levels not dependent upon the relative device sizes => Ratioless Transistors can be minimum size Regenerative Property Low output impedance Large Fan-out (albeit with degraded performance) Typical output resistance in kw range Digital ICs CMOS Inverter Digital ICs CMOS Inverter CMOS Properties () Extremely high input resistance (MOS transistor is near perfect insulator) nearly zero steady-state input current No direct path between power and ground under steady-state (but there always exists a path with finite resistance between the output and either or GND) no static power dissipation Propagation delay a function of load capacitance and resistance of transistors -545 Digital ICs CMOS Inverter NMOS Short Channel I-V Plot Recap I D (A) X V DS (V) V GS =.5 V V GS =. V V GS =.5 V V GS =. V NMOS transistor,.5 mm, L d =.5 mm, W/L =.5, =.5 V, V T =.4 V -545 Digital ICs CMOS Inverter Linear dependence -545 Digital ICs 3

4 July 5th, 4 PMOS Short Channel I-V Plot Recap l All polarities of all voltages and currents are reversed - V GS = -. V V GS = -.5 V V GS = -. V V DS (V) I D (A) Transforming PMOS I-V Plot I DSp = -I DSn V GSn = ; V GSp = - V DSn = ; V DSp = - = =.5 I Dn l NMOS and PMOS VTC must be put into a common coordinate set of,, and I Dn = =.5 V GS = -.5 V X -4 PMOS transistor,.5 mm, L d =.5 mm, W/L =.5, =.5 V, V T = -.4 V -545 Digital ICs CMOS Inverter 3 V GSp = - V GSp = -.5 Mirror around x-axis = + V GSp I Dn = -I Dp Horiz. shift over = + V DSp -545 Digital ICs CMOS Inverter 4 CMOS Inverter Load-Line Plot I Dn (A) PMOS X -4 NMOS.5 = V =.5 V.5 =. V = V (V) =.5 V =. V =.5 V = V =.5 V.5 =.5 V =. V =. V =.5 V =.5 V =.5 V = V CMOS.5 mm, W/L n =.5, W/L p = 4.5, =.5 V, V Tn =.4 V, V Tp = -.4 V -545 Digital ICs CMOS Inverter 5 CMOS Inverter VTC (V) * VTC = Voltage-Transfer Characteristics NMOS off PMOS res NMOS sat PMOS res NMOS sat PMOS sat = NMOS res PMOS sat NMOS res PMOS off (V) -545 Digital ICs CMOS Inverter Digital ICs 4

5 July 5th, 4 Robustness of CMOS Inverter Precise Values of Switching Threshold, V M V M is defined as the point where = Noise Margins Piece-Wise Linear Approximation Maximization Process Variations Device Variations Technology Scaling -545 Digital ICs CMOS Inverter 7 Switching Threshold At V M where =, both PMOS and NMOS transistors are in saturation (since V DS = V GS ) V M ª r /( + r) where r = k p V DSATp /k n V DSATn Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors Goal: To set V M = / (to maximize noise margins), so r ª ( W L) p W L ( ) n = ( ) ( ) k n 'V DSAT,n V M -V T,n -V DSAT,n / [ ] k p 'V DSAT,p - V M -V T,p -V DSAT,p / -545 Digital ICs CMOS Inverter 8 Switch Threshold Example Example: Simulated Results In our generic.5 micron CMOS process, using the process parameters from Table 3., at =.5V, and a minimum size NMOS device ((W/L) n of.5) NMOS PMOS V T (V) g(v.5 ) V DSAT (V).63 - k (A/V ) 5 x -6-3 x -6 l(v - ).6 -. V (V) M V (W/L) p (W/L) n = 5 x ( /) x x = x (.5.4./) (W/L) p = 3.5 x.5 = 5.5 for a V M of.5 V -545 Digital ICs CMOS Inverter 9..9 r = W p /W n Minimum Width-to-Length = Digital ICs CMOS Inverter -545 Digital ICs 5

6 July 5th, 4 Observations I V M is relatively insensitive to variations in device ratio Small Variations of the ratio do not significantly disturb VTC. Common Industry Practice to set W p smaller than the reuirement. Increasing the width of the PMOS moves V M towards Increasing the width of the NMOS moves V M toward GND -545 Digital ICs CMOS Inverter 3 V OH = V OL = GND VIL IL V VIH IH A piece-wise linear approximation of VTC Noise Margins: Determining V IH and V IL By definition, V IH and V IL are where gain d /d = - Slope = g V M Gain g = Slope NM H = - V IH NM L = V IL - GND Approximating: V IH = V M - V M /g V IL = V M + ( - V M )/g So high gain in the transition region is very desirable -545 Digital ICs CMOS Inverter CMOS Voltage Gain gain Gain is a strong function of the slopes of the currents in the saturation region, for = V M Determined only by technology parameters, especially channel length modulation (l). Only designer influence through supply voltage and V M (transistor sizing) Digital ICs CMOS Inverter 3 Example: VTC and Noise Margin For a.5mm, (W/L) p /(W/L) n = 3.4, (W/L) n =.5 (min size) =.5V V M ª.5 V, g = -7.5 V IL =. V, V IH =.3 V NM L = NM H =. Real Value V IL =.3 V, V IH =.45 V NM L =.3, NM H =.5 Output resistance fi Sensitivity of gate output with respect to noise low-output =.4 kw high-output = 3.3 kw Preferably as low as possible -545 Digital ICs CMOS Inverter Digital ICs 6

7 July 5th, 4 Observations II First-Order Analysis overestimates the gain Max. gain only 7 at V M Æ V IL =.7V, V IH =.33V Piecewise Linear Approximation is too overly optimistic Major contributor to deviation from the true gain CMOS inverter is a poor analog amplifier! One of the major differences between analog and digital designs is that digital circuits operate in the regions of extreme nonlinearity. Well-defined and well-separated high and low signals -545 Digital ICs CMOS Inverter 5 Vout(V).5.5 Impact of Process Variation on VTC.5 Bad PMOS Good Vin(V) variations (mostly) NMOSlProcess cause a shift in the switching threshold -545 Digital ICs CMOS Inverter 6 Nominal Good PMOS Bad NMOS Scaling the Supply Voltage Vout(V) (V) Vin(V) Reducing improves Gain But it deteriorates for very low -545 Digital ICs CMOS Inverter 7 Vout(V) Gain=- Practical Lower Bound: min > to 4 kt / Observations III Reducing the supply voltage has a positive impact on the energy dissipation But is also detrimental to the delay of the gate DC Characteristic becomes increasingly sensitive to device variations once supply and intrinsic voltages become comparable Scaling the supply voltage = reducing the swing Reduce internal noise (e.g., crosstalk) More susceptible to external noise that do not scale -545 Digital ICs CMOS Inverter Digital ICs 7

8 July 5th, 4 CMOS Inverter Dynamic Behavior Transient behavior of the gate is determined by the time it takes to charge and discharge the load capacitance,, through on-transistors Delay is a function of load capacitances and transistor on-resistances Getting as small as possible is crucial to the realization of high-performance CMOS circuits Transistor Capacitances Wire Capacitances Fanout Wire Resistances also become more important Digital ICs CMOS Inverter 9 Computing the Capacitances V Extrinsic DD M C M4 db C g4 C V gd out C db C w C g3 M M3 Interconnect Intrinsic Fanout Simplified Model -545 Digital ICs CMOS Inverter 3 Finding C gd : The Miller Effect M and M are either in cut-off or in saturation. The floating gate-drain capacitor is replaced by a capacitance-to-ground (gate-bulk capacitor). DV C gd M DV A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground whose value is two times the original value -545 Digital ICs CMOS Inverter 3 DV M DV C gd Diffusion Capacitances: C db and C db We can simplify the diffusion capacitance calculations by using a K e to linearize the nonlinear capacitor to the value of the junction capacitance under zero-bias.5 mm Process NMOS PMOS high-to-low K ebp C e = K e C j K esw.6.86 low-to-high K ebp K esw Digital ICs CMOS Inverter Digital ICs 8

9 July 5th, 4 Extrinsic Capacitances: C g3 and C g4 Example: Layout of Two Inverters Simplification of the actual situation Assumes all the components of C gate are between and GND (or ) Assumes the channel capacitances of the loading gates are constant The extrinsic, or fan-out, capacitance is the total gate capacitance of the loading gates M 3 and M 4. PMOS.5/.5 Polysilicon NMOS.375/.5 In Out GND Metal l =.5 AD = Drain Area PD = Drain Perimeter AS = Source Area PS = Source Perimeter Minimum Drawn Length C fan-out = C gate (NMOS) + C gate (PMOS) = (C GSOn + C GDOn + W n L n C ox ) + (C GSOp + C GDOp + W p L p C ox ).5 mm NMOS PMOS W/L.375/.5.5/.5 AD (mm ).3.7 PD (mm) AS (mm ).3.7 PS (mm) Digital ICs CMOS Inverter Digital ICs CMOS Inverter 34 Example: Components of (.5 mm) C Term C gd Expression Value (ff) HÆL Value (ff) LÆH C gdn W n.3.3 C gd C gdp W p.6.6 C db K ebpn AD n C j + K eswn PD n C jsw.66.9 C db K ebpp AD p C j + K eswp PD p C jsw.5.5 C g3 ( C gdn )W n + C ox W n L n C g4 ( C gdp )W p + C ox W p L p.8.8 C w from extraction.. Â Wiring Capacitance The wiring capacitance depends upon the length and width of the connecting wires and is a function of the fan-out from the driving gate and the number of fan-out gates. Wiring capacitance is growing in importance with the scaling of technology Digital ICs CMOS Inverter Digital ICs CMOS Inverter Digital ICs 9

10 July 5th, 4 Inverter Propagation Delay R p = Charge Low to High = V DD Propagation delay is proportional to the time-constant of the network formed by the on-resistance and the load capacitance t p = f(r on, ) t plh =.69 R ep t phl =.69 R en t p = t + t phl plh Ê R =.69C en + R ep ˆ L Á Ë Discharge -545 Digital ICs CMOS Inverter 37 R n High to Low To eualize rise and fall times make the on-resistance of the NMOS and PMOS approximately eual. Inverter Transient Response (.5 µm) Vin, Vout(V) t phl Simulation t(psec) t plh t phl = 39.9 psec and t plh = 3.7 psec Analysis =.5V W/L n =.5 W/L p = 4.5 R en = 3 kw /.5 R ep = 3 kw /4.5 t phl = 36 psec t plh = 9 psec t p = (36+9)/ = 3.5 psec Analysis results is too optimistic ~ % better -545 Digital ICs CMOS Inverter 38 Inverter Propagation Delay, Revisited To see how a designer can optimize the delay of a gate, we have to expand R e in the delay euation. tp(normalized) (V) t phl =.69 R en =.69(3C )/(4I DSATn ) t phl ª.5 W L -545 Digital ICs CMOS Inverter 39 ( ) n k n V DSATn Minimizing Propagation Delay Reduce Keep the drain diffusion as small as possible Increase W/L ratio of the transistor Most powerful and effective way Watch out for self-loading! When the intrinsic capacitance dominates Increase Trade off energy efficiency for performance Very minimal improvement above a certain level Reliability concerns enforce a firm upper bound on -545 Digital ICs CMOS Inverter Digital ICs

11 July 5th, 4 PMOS-to-NMOS Ratio So far PMOS and NMOS have been sized such that their R e s match (ratio of 3 to 3.5) symmetrical VTC eual high-to-low and low-to-high propagation delays If speed is the only concern, reduce the width of the PMOS device! widening the PMOS degrades the t phl due to larger parasitic capacitance Ê C ˆ b = (W/L) p /(W/L) b n opt = r + W Á Ë C dn + C Cgn r = R ep /R en resistance ratio of identically-sized PMOS and NMOS -545 Digital ICs CMOS Inverter 4 PMOS-to-NMOS Ratio Effects tp(psec) t plh b t p t phl b of.4 (= 3 kw/3 kw) gives symmetrical response b opt ~ Analytic Simulated When wire capacitance is negligible (C dn +C gn >> C W ), b opt = r If wire capacitance dominates then larger value of b must be used -545 Digital ICs CMOS Inverter 4 Device Sizing for Performance Divide capacitive load,, into C int : intrinsic - diffusion and Miller effect C ext : extrinsic - wiring and fanout t p =.69 R e C int ( + C ext /C int ) = t p ( + C ext /C int ) where t p =.69 R e C int is the intrinsic (unloaded) delay of the gate Widening both PMOS and NMOS by a factor S reduces R e by an identical factor (R e = R ref /S), but raises the intrinsic capacitance by the same factor (C int = SC iref ) t p =.69 R ref C iref ( + C ext /(SC iref )) = t p ( + C ext /(SC iref )) Observation IV Intrinsic Delay of the inverter t p is independent of the sizing of the gate; t p can be determined purely by technology and inverter layout With no load the increased drive strength of the gate is totally offset by the increased capacitance Any S sufficiently larger than (C ext /C int ) would yield a much better performance gain with a substantial area increase -545 Digital ICs CMOS Inverter Digital ICs CMOS Inverter Digital ICs

12 July 5th, 4 Sizing Impacts on Delay tp(psec) for a fixed load S The majority of the improvement is already obtained for S = 5. Sizing factors larger than barely yield any extra gain (and cost significantly more area). self-loading effect (intrinsic capacitance dominates) -545 Digital ICs CMOS Inverter 45 Impact of Fanout on Delay Extrinsic capacitance, C ext, is a function of the fanout of the gate the larger the fanout, the larger the external load. First determine the input loading effect of the inverter. Both C g and C int are proportional to the gate sizing, so C int = gc g is independent of gate sizing and t p = t p ( + C ext / gc g ) = t p ( + f /g) The delay of an inverter is a function of the ratio between its external load capacitance and its input gate capacitance: the effective fan-out f f = C ext /C g -545 Digital ICs CMOS Inverter 46 Inverter Chain Goal: to minimize the delay through an inverter chain In C g, N The delay of the j-th inverter stage is t p,j = t p ( + C g,j+ /(gc g,j )) = t p ( + f j / g) Overall Delay: t p = Ât p,j = t p  ( + C g,j+ /(gc g,j )) If is given How should the inverters be sized? How many stages are needed to minimize the delay? Out -545 Digital ICs CMOS Inverter 47 Sizing the Inverters in the Chain The optimum size of each inverter is the geometric mean of its neighbors meaning that if each inverter is sized up by the same factor f wrt the preceding gate, it will have the same effective fan-out and the same delay f = N N C g, = F where F represents the overall effective fan-out of the circuit (F = /C g, ) The minimum delay through the inverter chain is t p = Nt p + N ( F /g) The relationship between t p and F is linear for one inverter, suare root for two, etc Digital ICs CMOS Inverter Digital ICs

13 July 5th, 4 Example: Inverter Chain Sizing In C g, f = f = 4 /C g, has to be evenly distributed over N = 3 inverters /C g, = 8/ f = 3 8 = Out = 8 C g, -545 Digital ICs CMOS Inverter 49 Determining N: Optimal Number of Inverters What is the optimal value for N given F (=f N )? If the number of stages is too large, the intrinsic delay of the stages becomes dominate If the number of stages is too small, the effective fan-out of each stage becomes dominate The optimum N is found by differentiating the minimum delay expression divided by the number of stages and setting the result to, giving N N g + F - ( F lnf)/n = For g = (ignoring self-loading) N = ln (F) and the effective-fan out becomes f = e =.788 For g = (the typical case) the optimum effective fan-out (tapering factor) turns out to be close to Digital ICs CMOS Inverter 5 Optimum Effective Fan-Out Example: Inverter (Buffer) Staging Fopt g f Choosing f larger than optimum has little effect on delay and reduces the number of stages (and area). Common practice to use f = 4 (for g = ) But too many stages has a substantial negative impact on delay -545 Digital ICs CMOS Inverter 5 Normalized Delay C g, = = 64 C g, 8 C g, = = 64 C g, 4 6 C g, = = 64 C g, C g, = = 64 C g, N f t p Digital ICs CMOS Inverter Digital ICs 3

14 July 5th, 4 Impact of Buffer Staging for Large F (g = ),, Unbuffered, Two Stage Chain Impressive speed-ups with optimized cascaded inverter chain for very large capacitive loads Digital ICs CMOS Inverter Opt. Inverter Chain Input Signal Rise/Fall Time In reality, the input signal changes gradually (and both PMOS and NMOS conduct for a brief time). This affects the current available for charging/discharging and impacts propagation delay. t p increases linearly with increasing input slope, t s, once t s > t p t s is due to the limited driving capability of the preceding gate -545 Digital ICs CMOS Inverter 54 tp(psec) t s = input signal slope t S (psec) for a minimum-size inverter with a fan-out of a single gate Design Challenge A gate is never designed in isolation: its performance is affected by both the fan-out and the driving strength of the gate(s) feeding its inputs. (Revised t p expression) t i p = ti step + h ti- step (h ª.5) Keep signal rise times smaller than or eual to the gate propagation delays. good for performance good for power consumption Keeping rise and fall times of the signals small and of approximately eual values is one of the major challenges in high-performance designs - slope engineering Digital ICs CMOS Inverter 55 Delay with Long Interconnect When gates are farther apart, wire capacitance and resistance can no longer be ignored. c int (r w, c w, L) t p =.69R dr C int + (.69R dr +.38R w )C w +.69(R dr +R w )C fan where R dr = (R en + R ep )/ Wire delay rapidly becomes the dominant factor (due to the uadratic term) in the delay budget for longer wires Digital ICs CMOS Inverter 56 c fan t p =.69R dr (C int +C fan ) +.69(R dr c w +r w C fan )L +.38r w c w L -545 Digital ICs 4

15 July 5th, 4 Where Does Power Go? Static Power Consumption Ideally zero for static CMOS but in the real world.. Leakage Current Loss Diodes and Transistors constantly losing charge Dynamic Power Consumption Charging/Discharging Capacitances Major Source of Power Dissipation in CMOS Circuits Direct-Path Current Loss Short circuit between Power Rail during Switching -545 Digital ICs CMOS Inverter 57 Dynamic Power Consumption Energy Supplied/Cycle = Energy Stored/Cycle = i VDD (t) P dyn = Energy/cycle * f clk -545 Digital ICs CMOS Inverter 58 Ú i VDD (t) dt = * V DD Ú i VDD (t)v out (t)dt = * V DD / = * * f clk Switching Activity Power dissipation does not depend on the size of the devices but depends on how often the circuit is switched. Switching Activity freuency of energy-consuming transition = f Æ Clock Gate output P dyn = * * f Æ = * * P Æ * f clk = C eff * * f clk Lowering Dynamic Power Lowering Physical Capacitance Capacitance: Function of fan-out, wire length, transistor sizes Activity factor: How often, on average, do gates switch? P dyn = P Æ f Quadratic Effect Supply Voltage: Has been dropping with successive generations Clock freuency: Increasing P Æ =.5, f Æ = f clk / 4 Effective Capacitance C eff = Average Capacitance Switched per clock cycle Reduction can be obtained only at Logic and Architectural Abstraction Levels -545 Digital ICs CMOS Inverter Digital ICs CMOS Inverter Digital ICs 5

16 I peak (A) July 5th, 4 Short Circuit Power Consumption Short Circuit Currents Determinates t sc E sc = t sc I peak P Æ I sc P sc = t sc I peak f Æ Finite slope of the input signal causes a direct current path between and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting (active) Digital ICs CMOS Inverter 6 t sc = Duration of the slope of the input signal I peak determined by the saturation current of the PMOS and NMOS transistors which depend on their sizes, process technology, temperature, etc. strong function of the ratio between input and output slopes a function of -545 Digital ICs CMOS Inverter 63 Impact of on P sc I peak as a Function of I sc ª Large capacitive load Output fall time significantly larger than input rise time. I sc ª I max Small capacitive load -545 Digital ICs CMOS Inverter 64 Output fall time substantially smaller than input rise time. x x - time (sec) 5 psec input slope = ff = ff = 5 ff When load capacitance is small, I peak is large. Short circuit dissipation is minimized by matching the rise/fall times of the input and output signals - slope engineering Digital ICs CMOS Inverter Digital ICs 6

17 July 5th, 4 P sc as a Function of Rise/Fall Times Static (Leakage) Power Consumption P normalized = 3.3 V =.5 V t sin /t sout W/L p =.5 mm/.5 mm W/L n =.375 mm/.5 mm = 3 ff =.5V When load capacitance is small (t sin /t sout > for > V) the power is dominated by P sc If < V Tn + V Tp then P sc is eliminated since both devices are never on at the same time. normalized wrt zero input rise-time dissipation -545 Digital ICs CMOS Inverter 66 Gate leakage VDD = P stat = I stat Drain junction leakage Sub-threshold current dominant factor. All leakages increase exponentially with temperature Junction leakage doubles every 9C Sub-threshold current becomes more concern in vdsm The closer the threshold voltage to zero, the larger the leakage current at V GS = V (when NMOS off) -545 Digital ICs CMOS Inverter 67 Leakage as a Function of V T Continued scaling of supply voltage and the subseuent scaling of threshold voltage will make sub-threshold conduction a dominant component of power dissipation. ID (A).E-.E-4.E-6.E-8.E-.E V GS (V) VT=.4V VT=.V An 9mV/decade V T roll-off - so each 55mcrease in V T gives 3 orders of magnitude reduction in leakage (but adversely affects performance) -545 Digital ICs CMOS Inverter 68 TSMC Processes Leakage and VT From MPR, June, pp. 9 Performance of various TSMC processes (G generic, LP low power, ULP ultra low power, HS high speed) V dd T ox (effective) L gate I DSat (n/p) (ma/mm) I off (leakage) (ra/mm) V Tn FET Perf. (GHz) CL8 G.8 V 4 Å.6 mm 6/6.4 V 3 CL8 LP.8 V 4 Å.6 mm 5/ V CL8 ULP.8 V 4 Å.8 mm 3/ V 4 Å CL5 HS.5 V 9 Å. mm 86/37,8.9 V CL3 HS. V 4 Å.8 mm 9/4 3,.5 V -545 Digital ICs CMOS Inverter 69 4 CL8 HS V.3 mm 78/ V Digital ICs 7

18 July 5th, 4 Exponential Increase in Leakages Energy and Power Euations Ileakage(nA/mm) Leakage currents double every degree increase in temperature Temperature (C). mm.3 mm.8 mm.5 mm The Leakage Power is six orders of magnitude smaller than the dynamic power (at room temperature) -545 Digital ICs CMOS Inverter 7 E = P Æ + t sc I peak P Æ + I leakage T clock Dynamic power (~9% today and decreasing relatively) f Æ = P Æ * f clock P = f Æ + t sc I peak f Æ + I leakage Short-circuit power (~8% today and decreasing absolutely) Leakage power (~% today and increasing) -545 Digital ICs CMOS Inverter 7 Sizing for Minimum Energy In C g Goal: Minimize Energy of the whole circuit Design parameters: f and t p t pref of circuit with f = and = V ref Overall Effective Fan-out F = C ext /C g Ê Ê t p = t p + f ˆ Á Ë g + Ê + F ˆ ˆ Á Á Ë fg Ë -545 Digital ICs CMOS Inverter 7 f Out C ext Intrinsic Delay of the inverter t p ~ t /(t - V TE ) Sizing for Minimum Energy II Performance Constraint (g=) t p t pref = t p t pref Ê + f + F ˆ Á Ë f ( 3 + F) = V ref Energy for single Transition E = V DD C g + g E E ref Ê + f + F ˆ Á V ref -V TE Ë f = -V TE ( 3 + F) [( )( + f ) + F] = V Ê ˆ Ê DD + f + F ˆ Á Ë V Á ref Ë 4 + F -545 Digital ICs CMOS Inverter Digital ICs 8

19 July 5th, 4 Sizing for Minimum Energy III (V) F= f Digital ICs CMOS Inverter 74 E/E ref Optimum sizing occurs at f opt = F Increasing device sizes beyond f opt increase self-loading factor Deteriorate performance and reuire increase in supply voltage.5.5 f Observation V Device sizing, combined with supply voltage reduction, is very effective in reducing the energy consumption For F =, minimum size device is the most effective For network with large effective fan-out (F >> ), a large reduction factor of almost can be obtained. Oversizing transistors beyond the optimal value results in a hefty increase of energy Unfortunately, a common approach in many today s design Optimal sizing factor for energy is smaller than the one for performance (delay), especially for large F For a fan-out of, f opt (energy) = 3.53, f opt (delay) = Digital ICs CMOS Inverter 75 Power-Delay and Energy-Delay Product Power-delay product (PDP) = P av * t p = ( )/ PDP is the average energy consumed per switching event (Watts * sec = Joule) Lower power design could simply be a slower design Energy-delay product (EDP) = PDP * t p = P av * t p EDP is the average energy consumed multiplied by the computation time reuired Takes into account that one can trade increased delay for lower energy/operation (e.g., via supply voltage scaling that increases delay, but decreases energy consumption) -545 Digital ICs CMOS Inverter 76 Energy-Delay Plot Energy-Delay (normalized) 5 5 Energy Energy-Delay. V V dd (V).5 micron Delay V Tn =.43 V, V DSATn =.63 V, V TEn =.74 V V Tp = -.4 V, V DSATp = - V, V TEp = -.9 V ac 3 EDP = L -V TE ( ) Where V TE = V T +V DSAT / opt = 3 V TE V TE (V Tn + V Tp )/ =.8 V opt = (3/)*.8 =. V -545 Digital ICs CMOS Inverter Digital ICs 9

20 July 5th, 4 Observation VI Voltage Dependence of the EDP Higher Supply Voltages reduce delay, but harm the energy. Vice Versa for low voltages opt simultaneously optimizes performance (delay) and energy For submicron technologies with V T in the range of.5 V, opt ~ V. opt does not necessarily represent the optimum voltage for a given design problem Goal of the design (speed or power) determinates the supply voltage -545 Digital ICs CMOS Inverter 78 Goals of Technology Scaling Make things cheaper: Want to sell more functions (transistors) per chip for the same money Build same products cheaper, sell the same part for less money Price per transistor has to be reduced But also want to be faster, smaller, lower power -545 Digital ICs CMOS Inverter 79 Technology Scaling Goals of scaling the dimensions by 3%: Reduce gate delay by 3% (increase operating freuency by 43%) Double transistor density Reduce energy per transition by 65% (5% power 43% increase in freuency Die size used to increase by 4% per generation Technology generation spans -3 years Technology Evolution (ITRS) International Technology Roadmap for Semiconductors (ITRS) ( Year of Introduction Technology node [nm] Supply [V] Wiring levels Max freuency [GHz],Local-Global Max mp power [W] Bat. power [W] Node years: 7/65nm, /45nm, 3/33nm, 6/3nm -545 Digital ICs CMOS Inverter Digital ICs CMOS Inverter Digital ICs

21 July 5th, 4 Technology Evolution (999) Technology Scaling Models Full Scaling (Constant Electrical Field) Ideal model - dimensions and voltage scale together by the same factor S Fixed Voltage Scaling Most common until recently Only dimensions scale, voltages remain constant General Scaling Most realistic for todays situation Voltages and dimensions scale with different factors -545 Digital ICs CMOS Inverter Digital ICs CMOS Inverter 83 Scaling Long Channel Devices Scaling Short Channel Devices -545 Digital ICs CMOS Inverter Digital ICs CMOS Inverter Digital ICs

22 July 5th, 4 Scaling Wire Capacitances Power Density vs. Scaling Factor S = Technology Scaling, U = Voltage Scaling, S L = Wire-length Scaling e c = impact of fringing and interwire capacitance Wire Delay Parameter Wire Capacitance Wire Energy Wire Delay/Intrinsic Delay Wire Energy/ Intrinsic Energy Relation WL/t R on C int C m V General Scaling e c /S L e c /S L e c /S L U e c S/S L e c S/S L Power Density (mw/mm ) µ k 3 µ k.7 Scaling Factor k?i normalized by 4mm design rule?j Power density increase approximately with S In correspondance with fixed-voltage scaling Recent Trend is more in line with Full-scaling Constant power density Accelerated scaling and more attention to powerreducing design techniues -545 Digital ICs CMOS Inverter Digital ICs CMOS Inverter 87 Evolution of Wire Delay and Gate Delay How the ratio of wire over intrinsic contributions will actually evolve is debatable -545 Digital ICs CMOS Inverter 88 Looking into the Future (Year ) Performance X/6 months TIP (terra instructions/s) 3 GHz clock Size No of transistors: Billion Die: 4*4 mm Power kw!! Leakage: /3 active Power -545 Digital ICs CMOS Inverter Digital ICs

23 July 5th, 4 Some Interesting Questions What will cause this model to break? When will it break? Will the model gradually slow down? Power and power density Leakage Process Variation -545 Digital ICs CMOS Inverter Digital ICs 3

The CMOS Inverter: A First Glance

The CMOS Inverter: A First Glance The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V

More information

Digital Integrated Circuits 2nd Inverter

Digital Integrated Circuits 2nd Inverter Digital Integrated Circuits The Inverter The CMOS Inverter V DD Analysis Inverter complex gate Cost V in V out complexity & Area Integrity and robustness C L Static behavior Performance Dynamic response

More information

THE INVERTER. Inverter

THE INVERTER. Inverter THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)

More information

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view) CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN

More information

5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1

5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1 5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design

More information

ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)

ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view) ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]

More information

Chapter 5. The Inverter. V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov Inverter

Chapter 5. The Inverter. V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov Inverter Chapter 5 The Inverter V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov.12 03 Objective of This Chapter Use Inverter to know basic CMOS Circuits Operations Watch for performance Index such as Speed (Delay calculation)

More information

CMOS Inverter (static view)

CMOS Inverter (static view) Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:

More information

Where Does Power Go in CMOS?

Where Does Power Go in CMOS? Power Dissipation Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking

More information

EEE 421 VLSI Circuits

EEE 421 VLSI Circuits EEE 421 CMOS Properties Full rail-to-rail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady

More information

Last Lecture. Power Dissipation CMOS Scaling. EECS 141 S02 Lecture 8

Last Lecture. Power Dissipation CMOS Scaling. EECS 141 S02 Lecture 8 EECS 141 S02 Lecture 8 Power Dissipation CMOS Scaling Last Lecture CMOS Inverter loading Switching Performance Evaluation Design optimization Inverter Sizing 1 Today CMOS Inverter power dissipation» Dynamic»

More information

The CMOS Inverter: A First Glance

The CMOS Inverter: A First Glance The CMOS Inverter: A First Glance V DD V in V out C L CMOS Properties Full rail-to-rail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power

More information

EECS 427 Lecture 11: Power and Energy Reading: EECS 427 F09 Lecture Reminders

EECS 427 Lecture 11: Power and Energy Reading: EECS 427 F09 Lecture Reminders EECS 47 Lecture 11: Power and Energy Reading: 5.55 [Adapted from Irwin and Narayanan] 1 Reminders CAD5 is due Wednesday 10/8 You can submit it by Thursday 10/9 at noon Lecture on 11/ will be taught by

More information

Lecture 4: CMOS review & Dynamic Logic

Lecture 4: CMOS review & Dynamic Logic Lecture 4: CMOS review & Dynamic Logic Reading: ch5, ch6 Overview CMOS basics Power and energy in CMOS Dynamic logic 1 CMOS Properties Full rail-to-rail swing high noise margins Logic levels not dependent

More information

COMP 103. Lecture 10. Inverter Dynamics: The Quest for Performance. Section 5.4.2, What is this lecture+ about? PERFORMANCE

COMP 103. Lecture 10. Inverter Dynamics: The Quest for Performance. Section 5.4.2, What is this lecture+ about? PERFORMANCE COMP 103 Lecture 10 Inverter Dynamics: The Quest for Performance Section 5.4.2, 5.4.3 [All lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated

More information

Dynamic operation 20

Dynamic operation 20 Dynamic operation 20 A simple model for the propagation delay Symmetric inverter (rise and fall delays are identical) otal capacitance is linear t p Minimum length devices R W C L t = 0.69R C = p W L 0.69

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 14 The CMOS Inverter: dynamic behavior (sizing, inverter

More information

Announcements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power

Announcements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power - Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 12-3pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances

More information

The Inverter. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic

The Inverter. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Inverter Revised from Digital Integrated Circuits, Jan M. Rabaey el, 2003 Propagation Delay CMOS

More information

CSE493/593. Designing for Low Power

CSE493/593. Designing for Low Power CSE493/593 Designing for Low Power Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.].1 Why Power Matters Packaging costs Power supply rail design Chip and system

More information

EE5311- Digital IC Design

EE5311- Digital IC Design EE5311- Digital IC Design Module 3 - The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 6, 2017 Janakiraman, IITM

More information

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br

More information

Power Dissipation. Where Does Power Go in CMOS?

Power Dissipation. Where Does Power Go in CMOS? Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit

More information

The Physical Structure (NMOS)

The Physical Structure (NMOS) The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two

More information

EE5311- Digital IC Design

EE5311- Digital IC Design EE5311- Digital IC Design Module 3 - The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 3, 2018 Janakiraman, IITM

More information

Digital Microelectronic Circuits ( ) The CMOS Inverter. Lecture 4: Presented by: Adam Teman

Digital Microelectronic Circuits ( ) The CMOS Inverter. Lecture 4: Presented by: Adam Teman Digital Microelectronic Circuits (361-1-301 ) Presented by: Adam Teman Lecture 4: The CMOS Inverter 1 Last Lectures Moore s Law Terminology» Static Properties» Dynamic Properties» Power The MOSFET Transistor»

More information

Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]

Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an N-Switch, the

More information

EE115C Winter 2017 Digital Electronic Circuits. Lecture 6: Power Consumption

EE115C Winter 2017 Digital Electronic Circuits. Lecture 6: Power Consumption EE115C Winter 2017 Digital Electronic Circuits Lecture 6: Power Consumption Four Key Design Metrics for Digital ICs Cost of ICs Reliability Speed Power EE115C Winter 2017 2 Power and Energy Challenges

More information

ASIC FPGA Chip hip Design Pow Po e w r e Di ssipation ssipa Mahdi Shabany

ASIC FPGA Chip hip Design Pow Po e w r e Di ssipation ssipa Mahdi Shabany ASIC/FPGA Chip Design Power Di ssipation Mahdi Shabany Department tof Electrical ti lengineering i Sharif University of technology Outline Introduction o Dynamic Power Dissipation Static Power Dissipation

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

Check course home page periodically for announcements. Homework 2 is due TODAY by 5pm In 240 Cory

Check course home page periodically for announcements. Homework 2 is due TODAY by 5pm In 240 Cory EE141 Fall 005 Lecture 6 MOS Capacitances, Propagation elay Important! Check course home page periodically for announcements Homework is due TOAY by 5pm In 40 Cory Homework 3 will be posted TOAY ue Thursday

More information

EECS 141: FALL 05 MIDTERM 1

EECS 141: FALL 05 MIDTERM 1 University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-1:3 Thursday, October 6, 6:3-8:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION

More information

ECE321 Electronics I

ECE321 Electronics I ECE31 Electronics Lecture 1: CMOS nverter: Noise Margin & Delay Model Payman Zarkesh-Ha Office: ECE Bldg. 30B Office hours: Tuesday :00-3:00PM or by appointment E-mail: payman@ece.unm.edu Slide: 1 CMOS

More information

MOS Transistor Theory

MOS Transistor Theory CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

More information

VLSI Design and Simulation

VLSI Design and Simulation VLSI Design and Simulation CMOS Inverters Topics Inverter VTC Noise Margin Static Load Inverters CMOS Inverter First-Order DC Analysis R p V OL = 0 V OH = R n =0 = CMOS Inverter: Transient Response R p

More information

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.

More information

ECE 342 Solid State Devices & Circuits 4. CMOS

ECE 342 Solid State Devices & Circuits 4. CMOS ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input

More information

MOSFET and CMOS Gate. Copy Right by Wentai Liu

MOSFET and CMOS Gate. Copy Right by Wentai Liu MOSFET and CMOS Gate CMOS Inverter DC Analysis - Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max

More information

VLSI Design I; A. Milenkovic 1

VLSI Design I; A. Milenkovic 1 Why Power Matters PE/EE 47, PE 57 VLSI Design I L5: Power and Designing for Low Power Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka

More information

Digital Microelectronic Circuits ( )

Digital Microelectronic Circuits ( ) Digital Microelectronic ircuits (361-1-3021 ) Presented by: Dr. Alex Fish Lecture 5: Parasitic apacitance and Driving a Load 1 Motivation Thus far, we have learned how to model our essential building block,

More information

9/18/2008 GMU, ECE 680 Physical VLSI Design

9/18/2008 GMU, ECE 680 Physical VLSI Design ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design

More information

ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

More information

CHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS

CHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS CHAPTER 5 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 5. CMOS Logic Gate Circuits 5. Digital Logic Inverters 5.3 The CMOS Inverter 5.4 Dynamic Operation of the CMOS Inverter 5.5 Transistor Sizing 5.6 Power

More information

Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor

More information

EEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 8 Lecture #5: CMOS Inverter AC Characteristics Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Acknowledgments Slides due to Rajit Manohar from ECE 547 Advanced

More information

CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look

CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates epartment of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka )

More information

CMOS Technology for Computer Architects

CMOS Technology for Computer Architects CMOS Technology for Computer Architects Recap Technology Trends Lecture 2: Transistor Inverter Iakovos Mavroidis Giorgos Passas Manolis Katevenis FORTH-ICS (University of Crete) 1 2 Recap Threshold Voltage

More information

CMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties.

CMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties. CMOS Inverter: Steady State Response CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates R p V OL = V OH = V M = f(r n, R p ) epartment of Electrical and Computer Engineering University

More information

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B) 1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed

More information

DC and Transient Responses (i.e. delay) (some comments on power too!)

DC and Transient Responses (i.e. delay) (some comments on power too!) DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02 - CMOS Transistor Theory & the Effects of Scaling

More information

2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering

2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering 007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits Deog-Kyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we

More information

ENEE 359a Digital VLSI Design

ENEE 359a Digital VLSI Design SLIDE 1 ENEE 359a Digital VLSI Design & Logical Effort Prof. blj@ece.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler

More information

Lecture 6: DC & Transient Response

Lecture 6: DC & Transient Response Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins

More information

THE CMOS INVERTER CHAPTER. Quantification of integrity, performance, and energy metrics of an inverter Optimization of an inverter design

THE CMOS INVERTER CHAPTER. Quantification of integrity, performance, and energy metrics of an inverter Optimization of an inverter design chapter5.fm Page 176 Friday, January 18, 2002 9:01 M CHPTER 5 THE CMOS INVERTER Quantification of integrity, performance, and energy metrics of an inverter Optimization of an inverter design 5.1 Introduction

More information

DC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.

DC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr. DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-604 yrpeng@uark.edu Pass Transistors We have assumed source is

More information

Midterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.

Midterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!

More information

Digital Integrated Circuits

Digital Integrated Circuits Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Short-circuit current The CMOS inverter :

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 16 CMOS Combinational Circuits - 2 guntzel@inf.ufsc.br

More information

EE141Microelettronica. CMOS Logic

EE141Microelettronica. CMOS Logic Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit

More information

Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational

More information

EE5780 Advanced VLSI CAD

EE5780 Advanced VLSI CAD EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay

More information

Announcements. EE141- Spring 2003 Lecture 8. Power Inverter Chain

Announcements. EE141- Spring 2003 Lecture 8. Power Inverter Chain - Spring 2003 Lecture 8 Power Inverter Chain Announcements Homework 3 due today. Homework 4 will be posted later today. Special office hours from :30-3pm at BWRC (in lieu of Tuesday) Today s lecture Power

More information

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model - Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next

More information

DC & Transient Responses

DC & Transient Responses ECEN454 Digital Integrated Circuit Design DC & Transient Responses ECEN 454 DC Response DC Response: vs. for a gate Ex: Inverter When = -> = When = -> = In between, depends on transistor size and current

More information

Spiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp

Spiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp 2-7.1 Spiral 2 7 Capacitance, Delay and Sizing Mark Redekopp 2-7.2 Learning Outcomes I understand the sources of capacitance in CMOS circuits I understand how delay scales with resistance, capacitance

More information

Lecture 4: DC & Transient Response

Lecture 4: DC & Transient Response Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide

More information

Properties of CMOS Gates Snapshot

Properties of CMOS Gates Snapshot MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

MOS Transistor I-V Characteristics and Parasitics

MOS Transistor I-V Characteristics and Parasitics ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

More information

COMP 103. Lecture 16. Dynamic Logic

COMP 103. Lecture 16. Dynamic Logic COMP 03 Lecture 6 Dynamic Logic Reading: 6.3, 6.4 [ll lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP03

More information

CMPEN 411 VLSI Digital Circuits Spring 2012

CMPEN 411 VLSI Digital Circuits Spring 2012 CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 09: Resistance & Inverter Dynamic View [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

More information

Practice 7: CMOS Capacitance

Practice 7: CMOS Capacitance Practice 7: CMOS Capacitance Digital Electronic Circuits Semester A 2012 MOSFET Capacitances MOSFET Capacitance Components 3 Gate to Channel Capacitance In general, the gate capacitance is similar to a

More information

Lecture 6 Power Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010

Lecture 6 Power Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010 EE4800 CMOS Digital IC Design & Analysis Lecture 6 Power Zhuo Feng 6.1 Outline Power and Energy Dynamic Power Static Power 6.2 Power and Energy Power is drawn from a voltage source attached to the V DD

More information

Interconnect (2) Buffering Techniques.Transmission Lines. Lecture Fall 2003

Interconnect (2) Buffering Techniques.Transmission Lines. Lecture Fall 2003 Interconnect (2) Buffering Techniques.Transmission Lines Lecture 12 18-322 Fall 2003 A few announcements Partners Lab Due Times Midterm 1 is nearly here Date: 10/14/02, time: 3:00-4:20PM, place: in class

More information

Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003

Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003 6.12 - Microelectronic Devices and Circuits - Spring 23 Lecture 14-1 Lecture 14 - Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:

More information

EEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation

EEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW

More information

Lecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:30-8:00pm in 105 Northgate

Lecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:30-8:00pm in 105 Northgate EE4-Fall 2008 Digital Integrated Circuits Lecture VTCs and Delay Lecture # Announcements No lab today, Mon., Tues. Labs restart next week Midterm # Tues. Oct. 7 th, 6:30-8:00pm in 05 Northgate Exam is

More information

Objective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components

Objective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components Objective: Power Components Outline: 1) Acknowledgements 2) Objective and Outline 1 Acknowledgement This lecture note has been obtained from similar courses all over the world. I wish to thank all the

More information

Topic 4. The CMOS Inverter

Topic 4. The CMOS Inverter Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk Topic 4-1 Noise in Digital Integrated

More information

Lecture 2: CMOS technology. Energy-aware computing

Lecture 2: CMOS technology. Energy-aware computing Energy-Aware Computing Lecture 2: CMOS technology Basic components Transistors Two types: NMOS, PMOS Wires (interconnect) Transistors as switches Gate Drain Source NMOS: When G is @ logic 1 (actually over

More information

EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University

EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 9 Propagation delay Power and delay Tradeoffs Follow board notes Propagation Delay Switching Time

More information

ECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model

ECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model ECE 34 Electronic Circuits Lecture 35 CMOS Delay Model Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input

More information

EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 116 Lecture #3: CMOS Inverters MOS Scaling Rajeevan Amirtharajah University of California, Davis Jeff Parhurst Intel Corporation Outline Review: Inverter Transfer Characteristics Lecture 3: Noise Margins,

More information

CMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering

CMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering CMOS logic gates João Canas Ferreira University of Porto Faculty of Engineering March 2016 Topics 1 General structure 2 General properties 3 Cell layout João Canas Ferreira (FEUP) CMOS logic gates March

More information

COMBINATIONAL LOGIC. Combinational Logic

COMBINATIONAL LOGIC. Combinational Logic COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino np-cmos Combinational vs. Sequential Logic In Logic

More information

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Dynamic Logic Introduction Digital IC EE141 2 Dynamic logic outline Dynamic logic principle Dynamic logic

More information

4.10 The CMOS Digital Logic Inverter

4.10 The CMOS Digital Logic Inverter 11/11/2004 section 4_10 The CMOS Digital Inverter blank.doc 1/1 4.10 The CMOS Digital Logic Inverter Reading Assignment: pp. 336346 Complementary MOSFET (CMOS) is the predominant technology for constructing

More information

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 10: February 15, 2018 MOS Inverter: Dynamic Characteristics Penn ESE 570 Spring 2018 Khanna Lecture Outline! Inverter Power! Dynamic Characteristics

More information

ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 342 Electronic Circuits. 3. MOS Transistors ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to

More information

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective Digital Integrated Circuits Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Introduction Digital IC Dynamic Logic Introduction Digital IC 2 EE141 Dynamic

More information

5. CMOS Gate Characteristics CS755

5. CMOS Gate Characteristics CS755 5. CMOS Gate Characteristics Last module: CMOS Transistor theory This module: DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Transistor ehavior 1) If the width of a transistor

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 10: February 16, 2016 MOS Inverter: Dynamic Characteristics Lecture Outline! Review: Symmetric CMOS Inverter Design! Inverter Power! Dynamic

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University

EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 8 Power Dissipation in CMOS Gates Power in CMOS gates Dynamic Power Capacitance switching Crowbar

More information

Interconnect (2) Buffering Techniques. Logical Effort

Interconnect (2) Buffering Techniques. Logical Effort Interconnect (2) Buffering Techniques. Logical Effort Lecture 14 18-322 Fall 2002 Textbook: [Sections 4.2.1, 8.2.3] A few announcements! M1 is almost over: The check-off is due today (by 9:30PM) Students

More information