MOS Transistor Theory


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1 CHAPTER 3 MOS Transistor Theory
2 Outline 2 1. Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models
3 MOS Transistor symbols Introduction 3 nmos symbols pmos symbols
4 MOS Structure 4 Accumulation Mode Depletion Mode Inversion Mode
5 Cutoff nmos Operation Regions 5 V gs < V t : no channel Linear V gs > V t, V gd > V t : linear resistor Saturation V gs > V t, V gd < V t : channel pinchoff
6 Outline 6 1. Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models
7 MOS Channel Charge Q C V V C V V V channel g gc t g gs ds t C WL t C WL g ox ox ox Qchannel L E, E Vds / L, Ids, tchannel t channel
8 Q C WL V V V 1 channel gs 2 ds t ds ox E, E V / L, 2 L L L E V I Q t channel channel, t ds ds channel Ideal IV Equations 8 L Ideal IV equation I ds Q t channel channel Qchannel L/ W Vds C V V V L 2 Vds Vgs Vt Vds 2 ox gs t ds Ids V V V 2 V 2 0 V 2 gs Vt gs t ds ds V gs V t V V V V ds dsat gs t V V V V ds dsat gs t cutoff linear saturation
9 Ideal IV Characteristics 9 nmos IV pmos IV
10 Outline Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models
11 Nonideal IV Effects 11 Velocity saturation: at high V ds, the carrier velocity is not proportional to lateral field. I ds decrease. Mobility degradation: at high V gs, the carrier scatter more and mobility decrease. I ds decrease. Channel length modulation effect: at high V ds, depletion of S/D, effective L. I ds increase. Subthreshold conduction: V gs < V t, I ds is exponentially dropoff instead of abruptly becoming zero. Drain/Source leakage: reverse diode junction leakage. Nonzero gate current I g : carriers tunneling effect. Body effect: threshold voltage V t is influence by V bs (bodytosource voltage).
12 Velocity Saturation 12 Carrier velocity : nonlinearly proportional to lateral electrical field before velocity saturation E 1E E lat lat sat : carrier velocity : mobility E V L : lateral electrical field E lat sat ds sat I ds will saturate due to velocity saturation, it depends on channel length L and applied V ds. Qchannel Qchannel I C W V V t L/ ds ox gs t sat channel sat
13 Ids I dsat 0 V V I dsat ds dsat αpower Law Model 13 αpower Law Model: piecelinear model to illustrate MOSs IV characteristic with velocity saturation. V V V gs ds ds Idsat Pc Vgs V t 2 V t V V dsat dsat cutoff linear saturation, V /2 dsat P Vgs V t Empirical parameters: Pc, P, Because of μ p < μ n, pmos experience less velocity saturation than nmos, therefore α p > α n Mobility degradation is modeled by a μ eff < μ, and the it can be included in the parameter α
14 Channel Length Modulation 14 Effective channel length: is reduced due the wider depletion region at high V ds L L L eff d The IV equation at saturation region with channel length modulation effect. λ is the empirical parameter 2 Vgs Vt Ids 1 Vds, / L 2 With shorter L, λ, result in output resistance, then MOSFET s intrinsic gain
15 Body Effect 15 The threshold voltage V t is increased by positive V sb. V sb < 0, V t, OFF leakage Design tradeoff N A Vt Vt 0 [ 2 s Vsb 2 s ], s 2T ln n V t0 : the threshold voltage for V sb = 0 φ f : fabricationprocess parameter i t ox ox 2qN A si 2qN C ox A si γ : Bodyeffect parameter (fabricationprocess parameter) N A : Doping concentration of ptype substrate ε s : permittivity of silicon=11.7 ε 0
16 Subthreshold Conduction 16 Leakage current at subthreshold region V gs < V t : weak inversion Ids I e e V V V nt T ds0 1 gs t ds I ds0 e T Leakage current = 0, when V ds = 0. It increase exponentially with V gs. DrainInduced Barrier Lowering (DIBL) : the V t will be reduced by a positive V ds. It will worse the leakage at subthreshold. It acts like channel length modulation effect at active mode. VtV t Vds
17 Junction Leakage 17 S/D junction leakage from a reversebiased diode VD T ID IS e 1 Junction leakage used to be the storage time limitation. In modern transistor with shorter length, subthreshold leakage far exceed junction leakage.
18 Tunneling 18 Gate leakage: from carriers' tunneling through gate oxide. It is exponentially reverse proportional to gate oxide. HiK (dielectric constant) gate insulator is used to reduce it.
19 Temperature Dependence 19 T μ : T T T r Tr k T V t : V T V T k T T t t r t r T I OFF I ON T I dsat T The circuit performance is improved: subthreshold leakage, saturation velocity, mobility, junction capacitance. But breakdown voltage.
20 Geometry Dependence 20 Effective channel length and width L L X 2L eff drawn L D X L, X : Poly overetch W W W X 2W eff drawn W D L, W :Sourcedrian lateral diffusion Use identical and same orientation MOSFET to get a good matching. ex. Current mirror D D
21 Outline Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models
22 CV Characteristics 22 Gate capacitance: with advance technology, t ox, L, C permicron keeps constant. C C WL C W g ox permicron ox Cpermicron CoxL L tox Parasitic capacitance: C db and C sb are from reverse pn junction and proportional to S/D area.
23 MOS Gate Capacitance Model 23 Gate capacitance: it varies with channel behavior at different operation region C C WL 0 ox S/D overlap capacitance: C gs(overlap) & C gd(overlap) are from S/D lateral diffusion, don t confused with C gs & C gd C C W gs( overlap ) gd ( overlap ) gsol C C W gdol
24 C gc vs. V gs & V ds 24 C gc vs. V gs C gc vs. V ds
25 Gate Capacitance vs. V ds 25 Long channel device: C gd will becomes near 0 at saturation Short channel device: more C gd(overlap) and C gs(overlap) factor
26 DataDependent Gate Capacitance 26
27 Outline Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models
28 CMOS Inverter DC Characteristic I 28
29 CMOS Inverter DC Characteristic II 29 I ds vs. V ds (nmos & pmos) For pmos, I d, V gs, V ds, V th <0 pmos IV as loadline of nmos input device.
30 CMOS Inverter DC Characteristic III 30 V in V out DC transfer curve Railtorail operation V in I DD DC transfer curve Dynamic power dissipation
31 DC Response 31 DC Response: V out vs. V in for a gate Ex: Inverter When V in = 0 > V out = V DD When V in = V DD > V out = 0 In between, V out depends on transistor size and current By KCL, must settle such that I dsn = I dsp We could solve equations V in But graphical solution gives more insight V DD I dsp I dsn V out
32 Transistor Operation 32 Current depends on region of transistor behavior For what V in and V out are nmos and pmos in Cutoff? Linear? Saturation?
33 nmos Operation 33 Cutoff Linear Saturated V gsn < V gsn > V gsn > V dsn < V dsn > V DD V in I dsp I dsn V out
34 nmos Operation 34 Cutoff Linear Saturated V gsn < V tn V gsn > V tn V gsn > V tn V dsn < V gsn V tn V dsn > V gsn V tn V DD V in I dsp I dsn V out
35 nmos Operation 35 Cutoff Linear Saturated V gsn < V tn V gsn > V tn V gsn > V tn V dsn < V gsn V tn V dsn > V gsn V tn V DD V gsn = V in V dsn = V out V in I dsp I dsn V out
36 nmos Operation 33 Cutoff Linear Saturated V gsn < V tn V in < V tn V gsn > V tn V in > V tn V dsn < V gsn V tn V out < V in  V tn V gsn > V tn V in > V tn V dsn > V gsn V tn V out > V in  V tn V DD V gsn = V in V dsn = V out V in I dsp I dsn V out
37 pmos Operation 37 Cutoff Linear Saturated V gsp > V gsp < V gsp < V dsp > V dsp < V DD V in I dsp I dsn V out
38 pmos Operation 38 Cutoff Linear Saturated V gsp > V tp V gsp < V tp V gsp < V tp V dsp > V gsp V tp V dsp < V gsp V tp V DD V in I dsp I dsn V out
39 pmos Operation 39 Cutoff Linear Saturated V gsp > V tp V gsp < V tp V gsp < V tp V dsp > V gsp V tp V dsp < V gsp V tp V DD V gsp = V in  V DD V dsp = V out  V DD V tp < 0 V in I dsp I dsn V out
40 pmos Operation 40 Cutoff Linear Saturated V gsp > V tp V in > V DD + V tp V gsp < V tp V in < V DD + V tp V dsp > V gsp V tp V out > V in  V tp V gsp < V tp V in < V DD + V tp V dsp < V gsp V tp V out < V in  V tp V DD V gsp = V in  V DD V dsp = V out  V DD V tp < 0 V in I dsp I dsn V out
41 IV Characteristics 41 Make pmos is wider than nmos such that n = p V gsn5 I dsn V gsn4 V gsn3 V dsp V gsp1 V gsp2 V DD 0 V DD V gsn2 V gsn1 V gsp3 V dsn V gsp4 I dsp V gsp5
42 Current vs. V out, V in 42 V in0 V in5 I dsn, I dsp V in1 V in4 V in2 V in3 V in3 V in4 V in2 V in1 V out V DD
43 Load Line Analysis 43 For a given V in : Plot I dsn, I dsp vs. V out V out must be where currents are equal in V in0 V in5 I dsn, I dsp V in1 V in4 V in2 V in3 V DD I dsp V in3 V in4 V in2 V in1 V in I dsn V out V out V DD
44 Load Line Analysis 44 V in = 0 V in0 I dsn, I dsp V in0 V out V DD
45 Load Line Analysis 45 V in = 0.2V DD I dsn, I dsp V in1 V in1 V out V DD
46 Load Line Analysis 46 V in = 0.4V DD I dsn, I dsp V in2 V in2 V out V DD
47 Load Line Analysis 47 V in = 0.6V DD I dsn, I dsp V in3 V in3 V out V DD
48 Load Line Analysis 48 V in = 0.8V DD I dsn, I dsp V in4 V in4 V out V DD
49 Load Line Analysis 49 V in = V DD V in0 V in5 I dsn, I dsp V in1 V in2 V in3 V in4 V out V DD
50 Load Line Summary 50 V in0 V in5 I dsn, I dsp V in1 V in4 V in2 V in3 V in3 V in4 V in2 V in1 V out V DD
51 DC Transfer Curve 51 Transcribe points onto V in vs. V out plot V DD A B V in0 V in5 V in1 V in4 V out C V in2 V in3 V in3 V in4 V in2 V in1 0 D E V tn V DD /2 V DD +V tp V out V DD V in V DD
52 Operating Regions 52 Revisit transistor operating regions Region nmos pmos A B C D E V out V DD A B 0 C D E V tn V DD /2 V DD +V tp V in V DD
53 Operating Regions 53 Revisit transistor operating regions Region nmos pmos A Cutoff Linear B Saturation Linear C Saturation Saturation D Linear Saturation E Linear Cutoff V out V DD A B 0 C D E V tn V DD /2 V DD +V tp V in V DD
54 CMOS Inverter Operation 54
55 Beta Ratio Effect 55 β parameters and ratio C p p ox p C W L W L n n ox n ratio p n β ratio = 1: largest noise margin μ n > μ p, choose (W/L) p > (W/L) n to make β ratio = 1 β ratio > 1: HIskewed inverter, switching threshold > 0.5V DD β ratio < 1: LOskewed inverter, switching threshold < 0.5V DD
56 Noise Margin I 56 Noise margin definition The allowable noise voltage on the input that the output wont be corrupted. V V V V IH IL OH OL NM V V L IL OL NM V V H OH IH minimum HIGH input voltage maximum LOW input voltage minimum HIGH output voltage maximum LOW output voltage
57 Indeterminate region (forbidden zone) Noise Margin II 57 V V V : output unknown logic level IL in IH
58 β ratio > 1 β Ratio and Noise Margin 58 Switching threshold > 0.5V DD V IH NM H V IL NM L β ratio < 1 Switching threshold < 0.5V DD V IH NM H V IL NM L Noise is scaled with V DD VDD, smaller NM is acceptable.
59 Ratioed Inverter Transfer Function I 59 nmos inverters with resistive of constant current load Transfer function depends on the ratio of pulldown to the pullup transistor (static load).
60 Ratioed Inverter Transfer Function II 60 PseudonMOS inverters with turnon pmos as load TurnON pmos is made by a depletion mode nmos in pure nmos process. Dissipating static power when V o = LOW Poor NM but smaller area & input capacitance loading
61 Pass Transistor DC Characteristic 61 Threshold drop nmos : can NOT pass 1 pmos : can NOT pass 0 Need to consider BODY EFFECT. ON resistance depends on V in Need to BOOST gate voltage with small V DD
62 Inverter + transmission gate Tristate Inverter 62 For the same size n and p devices, it is approximately half the speed of complementary CMOS inverter. The structure in (d) is suffered from A s toggle in tristate. Need to consider BODY EFFECT.
63 Outline Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models
64 Effective Resistance R 64 R: effective resistance of unit nmos (minimum W & L) An pmos has resistance 2R(or 3R) because of smaller mobility In linear region, it is inverse proportional to W/L and V gs 1 I ds 1 1 L 1 R Vds C W Vgs V t ox Vgs Vt C: gate capacitance of unit transistor (nmos & pmos) It is proportional to gate area W*L C: junction capacitance of S/D of unit transistor It is proportional to gate width W nmos of k times unit width has resistance R/k, gate capacitance kc and S/D capacitance kc.
65 RC Circuit Model 65 pmos of k times unit width has resistance 2R/k, gate capacitance kc and S/D capacitance kc nmos parasitic capacitors are referred to GND (pbody) and pmos parasitic capacitors are referred to VDD (nwell)
66 Inverter Propagation Delay 66 Fanoutof1 Inverter Choose pmos width size to be x2~x3 of that of nmos t R 6C 6RC pd
67 R of Transmission Gate 67 Effective resistance of transmission gate is the parallel combination of nmos and pmos It depends on the signal to be pass pmos pass 0 weakly with larger resistance 4R nmos pass 1 weakly with larger resistance 2R Usually choose same size of nmos/pmos in transmission gate Increase MOS size R C : need to check the tradeoff
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