CMOS Inverter (static view)


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1 Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review: The MOS Transistor CMOS Inverter: A First Look Source W Polysilicon Gate L Gate oxide Drain FieldOxide (SiO ) p substrate p+ stopper Bulk (Body) 3 4
2 CMOS Inverter: Steady State Response R p V OL = V OH = V M = f(r n, R p ) CMOS Properties Full railtorail swing high noise margins Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady state low output impedance (output resistance in kω range) large fanout (albeit with degraded performance) = R n = Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steadystate input current = = Vm is defined as Vin = Vout No direct path steadystate between power and ground no static power dissipation Propagation delay function of load capacitance and resistance of transistors 5 6 Review: Short Channel IV Plot (NMOS) I D (A) X 4.5 V GS =.5V V GS =.V.5 V GS =.5V.5 V GS =.V Linear dependence Review: Short Channel IV Plot (PMOS) All polarities of all voltages and currents are reversed  V GS = .V V GS = .5V V GS = .V V DS (V) I D (A) V DS (V) NMOS transistor,.5um, L d =.5um, W/L =.5, =.5V, V T =.4V 7 V GS = .5V PMOS transistor,.5um, L d =.5um, W/L =.5, =.5V, V T = .4V X 4 8
3 CMOS Inverter VTC CMOS Inverter VTC.5.5 NMOS off PMOS res NMOS sat PMOS res (V).5 (V).5 NMOS sat PMOS sat NMOS res PMOS sat NMOS res PMOS off 9 CMOS Inverter: Switch Model of Dynamic Behavior CMOS Inverter: Switch Model of Dynamic Behavior R p R p R n R n = = = = Gate response time is determined by the time to charge through R p (discharge through R n )
4 Relative Transistor Sizing When designing static CMOS circuits, balance the driving strengths of the transistors by making the PMOS section wider than the NMOS section to maximize the noise margins and obtain symmetrical characteristics Switching Threshold V M where = (both PMOS and NMOS in saturation since V DS = V GS ) V M r /( + r) where r = k p V DSATp /k n V DSATn Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors Want V M = / (to have comparable high and low noise margins), so want r (W/L) p k n V DSATn (V M V Tn V DSATn /) = (W/L) n k p V DSATp ( V M +V Tp +V DSATp /) 3 4 Switch Threshold Example In.5 micron CMOS process, a =.5V, and a minimum size NMOS device ((W/L) n of.5) V T (V) γ(v.5 ) V DSAT (V) k (A/V ) λ(v  ) NMOS x 6.6 PMOS x (W/L) p 5 x ( /) = x x = 3.5 (W/L) n 3 x (.5.4./) (W/L) p = 3.5 x.5 = 5.5 for a V M of.5v V M (V) Simulated Inverter V M ~3.4 (W/L) p /(W/L) n Note: xaxis is semilog V M is relatively insensitive to variations in device ratio setting the ratio to 3,.5 and gives V M s of.v,.8v, and.3v Increasing the width of the PMOS moves V M towards Increasing the width of the NMOS moves V M toward GND 5 6
5 Noise Margins Determining V IH and V IL CMOS Inverter VTC from Simulation 3 V OH = V OL = GND VIL V M A piecewise linear approximation of VTC VIH By definition, V IH and V IL are where d /d =  (= gain) NM H = V IH NM L = V IL  GND Approximating: V IH = V M V M /g V IL = V M + ( V M )/g So high gain in the transition region is very desirable 7 (V) um, (W/L) p /(W/L) n = 3.4 (W/L) n =.5 (min size) =.5V V M.5V, g = 7.5 V IL =.V, V IH =.3V NM L = NM H =. (actual values are V IL =.3V, V IH =.45V NM L =.3V & NM H =.5V) Output resistance lowoutput =.4kΩ highoutput = 3.3kΩ 8 Gain Determinates Impact of Process Variation on VTC Curve gain Gain is a strong function of the slopes of the currents in the saturation region, for = V M (+r) g (V M V Tn V DSATn /)(λ n  λ p ) Determined by technology parameters, especially channel length modulation (λ). Only designer influence through supply voltage and V M (transistor sizing). 9 (V) Bad PMOS Good NMOS Good PMOS Bad NMOS Nominal Process variations (mostly) cause a shift in the switching threshold
6 Scaling the Supply Voltage CMOS Inverter Layout (V).5.5 (V)..5. metal metal pdiff Out In metalpoly via polysilicon PMOS (4/.4 = 6/).5.5 Gain= Device threshold voltages are kept (virtually) constant Device threshold voltages are kept (virtually) constant metaldiff via GND NMOS (/.4 = 8/) ndiff metalmetal via
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