Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: CMOS Inverter: Visual VTC. Review: CMOS Inverter: Visual VTC


 Bernadette Hutchinson
 5 years ago
 Views:
Transcription
1 ESE 570: Digital Integrated Circuits and LSI Fundamentals Lec 0: February 4, 207 MOS Inverter: Dynamic Characteristics Lecture Outline! Review: Symmetric CMOS Inverter Design! Inverter Power! Dynamic Characteristics Delay 2 Review: CMOS Inverter: isual TC Review: CMOS Inverter: isual TC  out = in  T0p  out = in  T0p th T0p out = in  T0n th T0p out = in  T0n th th th T0n th T0n   th  th T0n IL  IH T0n IL IH 3 4 Review: CMOS Inverter: Design/Sizing Review: Noise Margin Example T 0n th = ( T 0 p ) = 2 T 0 p th # th Important design Eq. for CMOS inverter TC. Compute the noise margins for a symmetric CMOS inverter has been designed to achieve th = /2, where = 5 and T0n =  T0p =. If th is set to ideal case: th = 2 = 2 T 0 p 2 = 2 2 T 0 p # 2 # 2 ideal th If T0n =  T0p =  T0 (symmetric CMOS) NM H = NM L = 2.25 RECALL (with = 5 ). NM H, NM L > /4 =.25 = 2 T 0 p 2 = k If, also 2 2 T 0 = R symetric = µ = W n n W p = µ n # 2 # 2 T 0 µ p W p W n µ p 2. Ideal NM => NM H = NM L = 2.5 > /2 5 6
2 Power Inverter Power! P = I! Tricky part: Understanding I (pairing with correct ) 8 Static Current Switching Currents! P = I static! Dynamic current flow:! If both transistor on: Current path from dd to Gnd Short circuit current 9 0 Currents Summary Currents Summary! I changes over! I changes over! At least two components! At least two components I static no switching I static no switching I switch when switching I switch when switching and I sc and I sc CLK φ ramp_enable RAMP 2 2
3 Switching Currents Switching! I total (t) = I static (t)i switch (t) Dynamic Power! I switch (t) = I sc (t) (t) I static I sc 3 4 Charging Switching Energy focus on (t)! (t) why is it changing? I ds = f( ds, gs ) and gs, ds changing I DS ν sat C OX W GS T ( DSAT 2 ) W ) I DS = µ n C OX ( # L GS T ) DS 2, DS. 2  I sc I static 5 6 Switching Energy focus on (t) Switching Energy! Do we know what this is? (t) E = P(t) = I(t) dd = dd E = P(t) = I(t) dd = dd 7 8 3
4 Switching Energy Switching Energy! Do we know what this is?! Do we know what this is? Q = (t) Q = (t)! What is Q? E = P(t) = I(t) dd = dd E = P(t) = I(t) dd = dd 9 20 Switching Energy Switching Energy! Do we know what this is?! Do we know what this is? Q = (t) Q = (t)! What is Q? E = P(t) = I(t) dd = dd Q = C =! What is Q? E = P(t) = I(t) dd = dd Q = C = E = C dd 2 Capacitor charging energy 2 22 Switching Power! Every output switches 0# pay: E = C 2 Switching! P dyn = (# 0# trans) C 2 / Short Circuit Power! # 0# trans = ½ # of transitions! P dyn = (# trans) ½C 2 /
5 Short Circuit Power! Between TN and dd  TP Both N and P devices conducting Short Circuit Power! Between TN and dd  TP Both N and P devices conducting! Roughly: I sc in ddthp thn dd dd Isc 25 out 26 Peak Current Peak Current! I peak around dd /2 If TN = TP and sized equal rise/spring I DS ν sat C OX W GS T ( DSAT 2 )! I peak around dd /2 If TN = TP and sized equal rise/spring I DS ν sat C OX W GS T ( DSAT 2 ) I t ( peak sc 2 ) in ddthp thn dd in ddthp thn dd dd Isc dd Isc out 27 out 28 Peak Current! I peak around dd /2 If TN = TP and sized equal rise/spring I DS ν sat C OX W GS T ( DSAT 2 ) I t ( peak sc 2 ) # E = dd I peak t sc ( in 2 dd ddthp thn dd Isc Short Circuit Energy! Make it look like a capacitance, C SC Q=I t Q=C E = dd I peak t sc # # 2 E = dd Q SC E = dd (C SC dd ) = C SC 2 dd out
6 Short Circuit Energy! Every switch (0# and #0) Also dissipate shortcircuit energy: E = C 2 Dynamic Characteristics Different C = C sc C cs fake capacitance (for accounting) 3 32 Inverter Delay Inverter Delay! Caused by charging and discharging the capacitive What is the? Inverter Delay Inverter Delay C gb = C gbn C gbp C = C # dbn C# dbp C# gdn C# gdp C int C gb
7 Inverter Delay Inverter Delay n = fanout Usually C db >> C gd C sb >> C gs C C # dbn C# dbp C int C gb C C dbn C dbp C int nc gb Propogation Delay Definitions Propogation Delay Definitions 0 t t 0 50 = / Propogation Delay Definitions Rise/Spring Times
8 MOS Inverter Dynamic Performance! ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and C, estimate (or measure) the propagation delays! DESIGN: For given specs for the propagation delays and C, determine the MOS inverter schematic MOS Inverter Dynamic Performance! ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and C, estimate (or measure) the propagation delays! DESIGN: For given specs for the propagation delays and C, determine the MOS inverter schematic METHODS:. Average Current Model METHODS: 2. Differential Equation Model Δ C HL = C OH 50 i C d out d = C out i C τ PLH C Δ LH 50 OL Assume in ideal or τ PLH Assume in ideal MOS Inverter Dynamic Performance! ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and C, estimate (or measure) the propagation delays! DESIGN: For given specs for the propagation delays and C, determine the MOS inverter schematic METHODS: 3. st Order RC delay Model Method Average Current Model 0.69 C R n τ PLH 0.69 C R p Assume in ideal 45 Calculation of Propagation Delays Calculation of Propagation Delays Δ C HL = C OH 50 Δ C HL = C OH 50 τ PLH C Δ LH 50 OL τ PLH C Δ LH 50 OL
9 Calculation of Propagation Delays Calculation of Rise/Spring Times Δ C HL = C OH 50 τ fall C Δ 90 0 I avg, I avg,90 0 τ PLH C Δ LH 50 OL τ rise C Δ 0 90 I avg, I avg, Calculation of Rise/Spring Times Calculation of Rise/Spring Times τ fall C Δ 90 0 I avg, I avg,90 0 τ fall C Δ 90 0 I avg, I avg,90 0 τ rise C Δ 0 90 I avg, I avg,0 90 τ rise C Δ 0 90 I avg, I avg, Calculating Propagation Delays Method 2 Assume in is an ideal stepinput Differential Equation Model Two Cases. in abruptly rises => out Springs => 2. in abruptly Springs => out rises => τ PLH i DP  i Dn 54 9
10 Case : in Abruptly Rises  Case : in Abruptly Rises Case : in Abruptly Rises  Case : in Abruptly Rises Case : in Abruptly Rises  Recall: CMOS Inverter: isual TC  out = in  T0p th T0p out = in  T0n th out = T0n th T0n  th  T0n IL IH
11 Case : in Abruptly Rises  Case : in Abruptly Rises  saturation linear t 0 #t t #t 50 T 0 n /2 =C d out C T 0 n d out out = T0n d C out i Dn d = C out i Dn = t=t 50 out= /2 = C t=t 0 out= ) d out i Dn ( =C /2 ) d out C ) i Dn ( T 0 n i Dn ( T 0 n t 0 #t t #t 50 d out out = T0n 6 saturation: i Dn = 2 ( in )2,sat T 0 n C 2 ) 2 # T 0 n d out,sat = d 2 ( out T 0n )2 2C,sat = T 0n ) 2 62 Case : in Abruptly Rises  Case : in Abruptly Rises  saturation linear t 0 #t t #t 50 T 0 n /2 =C d out C T 0 n ( ) d out linear: i Dn = 2 ( ) 2 in T 0n out out /2,lin T 0 n ( 2 2( ) 2 T 0n out out # ),lin = 2C /2 k n #( 2 ) out 2 T 0 n out ),lin = 2C 2 ) ln out #( 2 ) out ) d out d out out= /2 out= T 0 n out = T0n 63,lin = 2C 2 ) ln # out ( 2 ) ( out ) C,lin = ) ln # 2 ) 2 ( 2 out= /2 out= T 0 n 64 Case : in Abruptly Rises  Case : in Abruptly Rises  saturation linear saturation linear t 0 #t t #t 50 T 0 n /2 =C d out C T 0 n d out out = T0n t 0 #t t #t 50 T 0 n /2 =C d out C T 0 n d out out = T0n 2C,sat = T 0n C τ ) 2 PHL,lin = ) ln 2 ) 2 # 2 2C,sat = T 0n ) 2 C,lin = ) ln 2 ) 2 # 2 2C = T 0n ) C 2 ) ln 2 ) 2 # 2 2C = T 0n ) C 2 ) ln 2 ) 2 # 2 R n 65 ) 2 =C T 0n ) ) ln # 2( ), T 0n (. 266
12 Case : in Abruptly Rises  Case : in Abruptly Rises  ) 2 =C T 0n ) ) ln # 2 ), (. 2  ) 2 =C T 0n ) ) ln # 2 ), (. 2  Recall from static CMOS Inverter: T 0n th = ( T 0 p ) = 2 T 0 p th # th Recall from static CMOS Inverter: T 0n th = ( T 0 p ) = 2 T 0 p th # th DESIGN: () th ; (2) ; (3) k p DESIGN: () th ; (2) ; (3) k p () th ; (2) τ PLH k p ; (3) k p Idea Admin! P tot = P static P dyn P sc Can t ignore Static Power (aka. Leakage power)! Propogation Delay Average Current Model Differential Equation Model st Order Model! HW 4 due Thursday, 2/
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 10: February 16, 2016 MOS Inverter: Dynamic Characteristics Lecture Outline! Review: Symmetric CMOS Inverter Design! Inverter Power! Dynamic
More information! Inverter Power. ! Dynamic Characteristics. " Delay ! P = I V. ! Tricky part: " Understanding I. " (pairing with correct V) ! Dynamic current flow:
ESE 570: Digital Integrated ircuits and LSI Fundamentals Lecture Outline! Inverter Power! Dynamic haracteristics Lec 10: February 15, 2018 MOS Inverter: Dynamic haracteristics " Delay 3 Power Inverter
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 10: February 15, 2018 MOS Inverter: Dynamic Characteristics Penn ESE 570 Spring 2018 Khanna Lecture Outline! Inverter Power! Dynamic Characteristics
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler
More informationMidterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 17: March 26, 2019 Energy Optimization & Design Space Exploration Penn ESE 570 Spring 2019 Khanna Lecture Outline! Energy Optimization! Design
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More informationLecture 14  Digital Circuits (III) CMOS. April 1, 2003
6.12  Microelectronic Devices and Circuits  Spring 23 Lecture 141 Lecture 14  Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:
More informationLecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More informationECE321 Electronics I
ECE31 Electronics Lecture 1: CMOS nverter: Noise Margin & Delay Model Payman ZarkeshHa Office: ECE Bldg. 30B Office hours: Tuesday :003:00PM or by appointment Email: payman@ece.unm.edu Slide: 1 CMOS
More informationEEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 8 Lecture #5: CMOS Inverter AC Characteristics Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Acknowledgments Slides due to Rajit Manohar from ECE 547 Advanced
More informationLecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:308:00pm in 105 Northgate
EE4Fall 2008 Digital Integrated Circuits Lecture VTCs and Delay Lecture # Announcements No lab today, Mon., Tues. Labs restart next week Midterm # Tues. Oct. 7 th, 6:308:00pm in 05 Northgate Exam is
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Total Power. Energy and Power Optimization. Worksheet Problem 1
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 20, 2018 Energy and Power Optimization, Design Space Exploration Lecture Outline! Energy and Power Optimization " Tradeoffs! Design
More informationThe Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two
More informationLecture 12 Circuits numériques (II)
Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More informationEE5311 Digital IC Design
EE5311 Digital IC Design Module 3  The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 6, 2017 Janakiraman, IITM
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 17: March 23, 2017 Energy and Power Optimization, Design Space Exploration, Synchronous MOS Logic Lecture Outline! Energy and Power Optimization
More informationENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)
ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More informationECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model
ECE 34 Electronic Circuits Lecture 35 CMOS Delay Model Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More informationLecture 13  Digital Circuits (II) MOS Inverter Circuits. March 20, 2003
6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 131 Lecture 13 Digital Circuits (II) MOS Inverter Circuits March 20, 2003 Contents: 1. NMOS inverter with resistor pullup (cont.) 2. NMOS
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2018 Final Monday, Apr 0 5 Problems with point weightings shown.
More informationPractice 7: CMOS Capacitance
Practice 7: CMOS Capacitance Digital Electronic Circuits Semester A 2012 MOSFET Capacitances MOSFET Capacitance Components 3 Gate to Channel Capacitance In general, the gate capacitance is similar to a
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown.
More information2007 Fall: Electronic Circuits 2 CHAPTER 10. DeogKyoon Jeong School of Electrical Engineering
007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits DeogKyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we
More information5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1
5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design
More information! Energy Optimization. ! Design Space Exploration. " Example. ! P tot P static + P dyn + P sc. ! SteadyState: V in =V dd. " PMOS: subthreshold
ESE 570: igital Integrated ircuits and VLSI undamentals Lec 17: March 26, 2019 Energy Optimization & esign Space Exploration Lecture Outline! Energy Optimization! esign Space Exploration " Example 3 Energy
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models MOS
More informationHightoLow Propagation Delay t PHL
HightoLow Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (nchannel) immediately switches from cutoff to saturation; the pchannel pullup switches from triode to
More informationCHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS
CHAPTER 5 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 5. CMOS Logic Gate Circuits 5. Digital Logic Inverters 5.3 The CMOS Inverter 5.4 Dynamic Operation of the CMOS Inverter 5.5 Transistor Sizing 5.6 Power
More informationEECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 111:3 Thursday, October 6, 6:38:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
More information! Dynamic Characteristics. " Delay
EE 57: Digital Integrated ircuits and LI Fundamentals Lecture Outline! Dynamic haracteristics " Delay Lec : February, 8 MO Inverter and Interconnect Delay 3 Review: Propogation Delay Definitions Dynamic
More informationEEE 421 VLSI Circuits
EEE 421 CMOS Properties Full railtorail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Restore Output. Pass Transistor Logic. How compare.
ESE 570: igital Integrated ircuits and VLSI undamentals Lec 16: March 19, 2019 Euler Paths and Energy asics & Optimization Lecture Outline! Pass Transistor Logic! Logic omparison! Transmission Gates! Euler
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V
More informationDC and Transient Responses (i.e. delay) (some comments on power too!)
DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02  CMOS Transistor Theory & the Effects of Scaling
More informationEEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #3: CMOS Inverters MOS Scaling Rajeevan Amirtharajah University of California, Davis Jeff Parhurst Intel Corporation Outline Review: Inverter Transfer Characteristics Lecture 3: Noise Margins,
More informationEE5311 Digital IC Design
EE5311 Digital IC Design Module 3  The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 3, 2018 Janakiraman, IITM
More informationMOSFET and CMOS Gate. Copy Right by Wentai Liu
MOSFET and CMOS Gate CMOS Inverter DC Analysis  Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD V in V out C L CMOS Properties Full railtorail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 8: February 9, 016 MOS Inverter: Static Characteristics Lecture Outline! Voltage Transfer Characteristic (VTC) " Static Discipline Noise Margins!
More informationCMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2016 Final Friday, May 6 5 Problems with point weightings shown.
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NORgate C = NOT (A or B)
1 Introduction to TransistorLevel Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationECE 342 Solid State Devices & Circuits 4. CMOS
ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More informationEE 560 MOS INVERTERS: DYNAMIC CHARACTERISTICS. Kenneth R. Laker, University of Pennsylvania
1 EE 560 MOS INVERTERS: DYNAMIC CHARACTERISTICS C gsp V DD C sbp C gd, C gs, C gb > Oxide Caps C db, C sb > Juncion Caps 2 S C in > Ineconnec Cap G B D C dbp V in C gdp V ou C gdn D C dbn G B S C in
More informationUniversity of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA
University of Pennsylvania Department of Electrical Engineering ESE 570 Midterm Exam March 4, 03 FORMULAS AND DATA. PHYSICAL CONSTANTS: n i = intrinsic concentration undoped) silicon =.45 x 0 0 cm 3 @
More informationAnnouncements. EE141 Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power
 Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 123pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 14 The CMOS Inverter: dynamic behavior (sizing, inverter
More information! MOS Capacitances. " Extrinsic. " Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February, 07 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance Model!
More informationEEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor NChannel MOSFET Built on ptype
More informationElectronic Devices and Circuits Lecture 15  Digital Circuits: Inverter Basics  Outline Announcements. = total current; I D
6.012  Electronic Devices and Circuits Lecture 15  Digital Circuits: Inverter asics  Outline Announcements Handout  Lecture Outline and Summary The MOSFET alpha factor  use definition in lecture,
More informationVLSI Design and Simulation
VLSI Design and Simulation CMOS Inverters Topics Inverter VTC Noise Margin Static Load Inverters CMOS Inverter FirstOrder DC Analysis R p V OL = 0 V OH = R n =0 = CMOS Inverter: Transient Response R p
More informationDigital Microelectronic Circuits ( ) Ratioed Logic. Lecture 8: Presented by: Mr. Adam Teman
Digital Microelectronic ircuits (36113021 ) Presented by: Mr. Adam Teman Lecture 8: atioed Logic 1 Motivation In the previous lecture, we learned about Standard MOS Digital Logic design. MOS is unquestionably
More informationEEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW
More informationCheck course home page periodically for announcements. Homework 2 is due TODAY by 5pm In 240 Cory
EE141 Fall 005 Lecture 6 MOS Capacitances, Propagation elay Important! Check course home page periodically for announcements Homework is due TOAY by 5pm In 40 Cory Homework 3 will be posted TOAY ue Thursday
More informationDigital Microelectronic Circuits ( )
Digital Microelectronic ircuits (36113021 ) Presented by: Dr. Alex Fish Lecture 5: Parasitic apacitance and Driving a Load 1 Motivation Thus far, we have learned how to model our essential building block,
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationDigital Integrated Circuits
Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Shortcircuit current The CMOS inverter :
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: 1st Order RC Delay Models. Review: TwoInput NOR Gate (NOR2)
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 14: March 1, 2016 Combination Logic: Ratioed and Pass Logic Lecture Outline! CMOS Gates Review " CMOS Worst Case Analysis! Ratioed Logic Gates!
More information9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Introduction Digital IC Dynamic Logic Introduction Digital IC 2 EE141 Dynamic
More informationCOMP 103. Lecture 16. Dynamic Logic
COMP 03 Lecture 6 Dynamic Logic Reading: 6.3, 6.4 [ll lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP03
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 3, 2016 Combination Logic: Ratioed & Pass Logic, and Performance Lecture Outline! CMOS NOR2 Worst Case Analysis! Pass Transistor
More informationEE115C Digital Electronic Circuits Homework #3
Electrical Engineering Department Spring 1 EE115C Digital Electronic Circuits Homework #3 Due Thursday, April, 6pm @ 56147E EIV Solution Problem 1 VTC and Inverter Analysis Figure 1a shows a standard
More informationECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120
ECE 6412, Spring 2002 Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 Problem 1O 2O 3 4 5 6 7 8 Score INSTRUCTIONS: This exam is closed book with four sheets of notes permitted. The exam consists of
More informationDigital Integrated Circuits A Design Perspective
igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational
More informationLecture 4: CMOS review & Dynamic Logic
Lecture 4: CMOS review & Dynamic Logic Reading: ch5, ch6 Overview CMOS basics Power and energy in CMOS Dynamic logic 1 CMOS Properties Full railtorail swing high noise margins Logic levels not dependent
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br
More informationDigital Microelectronic Circuits ( ) The CMOS Inverter. Lecture 4: Presented by: Adam Teman
Digital Microelectronic Circuits (3611301 ) Presented by: Adam Teman Lecture 4: The CMOS Inverter 1 Last Lectures Moore s Law Terminology» Static Properties» Dynamic Properties» Power The MOSFET Transistor»
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February 4, 2016 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance
More informationToday s lecture. EE141 Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
 Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
More informationMiscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]
Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an NSwitch, the
More informationEE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing
EE115C Winter 2017 Digital Electronic Circuits Lecture 3: MOS RC Model, CMOS Manufacturing Agenda MOS Transistor: RC Model (pp. 104113) S R on D CMOS Manufacturing Process (pp. 3646) S S C GS G G C GD
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 18: March 27, 2018 Dynamic Logic, Charge Injection Lecture Outline! Sequential MOS Logic " DLatch " Timing Constraints! Dynamic Logic " Domino
More informationName: Answers. Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015
University of Pennsylvania Department of Electrical and System Engineering CircuitLevel Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2015 Midterm 1 Monday, September 28 5 problems
More informationEECS 141 F01 Lecture 17
EECS 4 F0 Lecture 7 With major inputs/improvements From MaryJane Irwin (Penn State) Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationLecture 6: DC & Transient Response
Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins
More informationChapter 5. The Inverter. V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov Inverter
Chapter 5 The Inverter V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov.12 03 Objective of This Chapter Use Inverter to know basic CMOS Circuits Operations Watch for performance Index such as Speed (Delay calculation)
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationReview of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model
Content MOS Devices and Switching Circuits Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model A Cantoni 20092013 Digital Switching 1 Content MOS
More informationDigital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo
Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Dynamic Logic Introduction Digital IC EE141 2 Dynamic logic outline Dynamic logic principle Dynamic logic
More informationStep 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since
Step 1. Finding V M Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since V DSn = V M  0 > V M  V Tn V SDp = V DD  V M = (V DD  V M ) V Tp Equate drain
More informationCMOS scaling rules Power density issues and challenges Approaches to a solution: Dimension scaling alone Scaling voltages as well
6.01  Microelectronic Devices and Circuits Lecture 16  CMOS scaling; The Roadmap  Outline Announcements PS #9  Will be due next week Friday; no recitation tomorrow. Postings  CMOS scaling (multiple
More informationDC & Transient Responses
ECEN454 Digital Integrated Circuit Design DC & Transient Responses ECEN 454 DC Response DC Response: vs. for a gate Ex: Inverter When = > = When = > = In between, depends on transistor size and current
More informationPower Dissipation. Where Does Power Go in CMOS?
Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit
More informationEE 434 Lecture 33. Logic Design
EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The twoinverter loop X Y X
More informationDynamic operation 20
Dynamic operation 20 A simple model for the propagation delay Symmetric inverter (rise and fall delays are identical) otal capacitance is linear t p Minimum length devices R W C L t = 0.69R C = p W L 0.69
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded
More informationLecture 23. CMOS Logic Gates and Digital VLSI I
ecture 3 CMOS ogic Gates and Digital SI I In this lecture you will learn: Digital ogic The CMOS Inverter Charge and Discharge Dynamics Power Dissipation Digital evels and Noise NFET Inverter Cutoff Saturation
More informationLecture 4: DC & Transient Response
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide
More informationPassTransistor Logic
all 26 Digital tegrated ircuits nnouncements No new homework this week roject phase one due on Monday Midterm 2 next Thursday Review session on Tuesday Lecture 8 Logic Dynamic Logic EE4 EE4 2 lass Material
More information4.10 The CMOS Digital Logic Inverter
11/11/2004 section 4_10 The CMOS Digital Inverter blank.doc 1/1 4.10 The CMOS Digital Logic Inverter Reading Assignment: pp. 336346 Complementary MOSFET (CMOS) is the predominant technology for constructing
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 9 Propagation delay Power and delay Tradeoffs Follow board notes Propagation Delay Switching Time
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 2 Quality Metrics of Digital Design guntzel@inf.ufsc.br
More information