# CMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering

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1 CMOS logic gates João Canas Ferreira University of Porto Faculty of Engineering March 2016

2 Topics 1 General structure 2 General properties 3 Cell layout João Canas Ferreira (FEUP) CMOS logic gates March / 37

3 Static dual CMOS gates In1 In2 InN pull-up network PMOS F(In1, In2,..., InN) In1 In2 InN pull-down network NMOS Pull- and pull-down networks are dual of each other: series of switches parallel switches João Canas Ferreira (FEUP) CMOS logic gates March / 37

4 NND logic gate B B Out= B B Out João Canas Ferreira (FEUP) CMOS logic gates March / 37

5 NND logic gate B B Out= B B Out Pull-down network: G = B Pull-up network : F = + B = B direct path to Gnd direct path to V DD Generally (self-duality): G(In 1, In 2,...) = F(In 1, In 2,...) Out = G(In 1, In 2,...) João Canas Ferreira (FEUP) CMOS logic gates March / 37

6 NOR logic gate B B Out = +B C Out = +B+C B B C B Out João Canas Ferreira (FEUP) CMOS logic gates March / 37

7 Complex CMOS logic gate B C D Out = D+(B+C) D B C João Canas Ferreira (FEUP) CMOS logic gates March / 37

8 Building a complex CMOS logic gate Design the pull-down network Find hierarchically all sub-networks Switch parallel series by hierarchical order João Canas Ferreira (FEUP) CMOS logic gates March / 37

9 Building a complex CMOS logic gate Design the pull-down network Find hierarchically all sub-networks Switch parallel series by hierarchical order D B C João Canas Ferreira (FEUP) CMOS logic gates March / 37

10 Building a complex CMOS logic gate Design the pull-down network Find hierarchically all sub-networks Switch parallel series by hierarchical order D D B C B C 4 João Canas Ferreira (FEUP) CMOS logic gates March / 37

11 Building a complex CMOS logic gate Design the pull-down network Find hierarchically all sub-networks Switch parallel series by hierarchical order 2 D D B 4 C B C B C 4 D 1 João Canas Ferreira (FEUP) CMOS logic gates March / 37

12 Criteria for complex CMOS static gates Dual circuit is not necessarily obtained by series parallel. There may be several dual circuits. How to identify a good dual circuit? João Canas Ferreira (FEUP) CMOS logic gates March / 37

13 Criteria for complex CMOS static gates Dual circuit is not necessarily obtained by series parallel. There may be several dual circuits. How to identify a good dual circuit? Methods Use Karnaugh maps to identify dual circuit with good layout properties and reduced parasitics. Maximize the number of connections to V DD or Gnd Put delay critical transistors near the output node João Canas Ferreira (FEUP) CMOS logic gates March / 37

14 Example: carry generation (1) Carry output of a full adder: F(a, b, c) = ab + bc + ac Implement function G(a, b, c) = F 0-cover defines the pull-down circuit 1-cover defines the pull-up circuit B C cover: ab + bc + ac 1-cover: a b + b c + a c João Canas Ferreira (FEUP) CMOS logic gates March / 37

15 Examplo: carry generation (2) Pull-down circuit Maximize number of connections to V DD Critical signal (C) near output Factorize: ab + c(a + b) C B B João Canas Ferreira (FEUP) CMOS logic gates March / 37

16 Examplo: carry generation (3) Series/parallel dual pull-up circuit B C B João Canas Ferreira (FEUP) CMOS logic gates March / 37

17 Examplo: carry generation (3) Series/parallel dual pull-up circuit Pull-up circuit derived from 1-cover B B C B B C João Canas Ferreira (FEUP) CMOS logic gates March / 37

18 Topics 1 General structure 2 General properties 3 Cell layout João Canas Ferreira (FEUP) CMOS logic gates March / 37

19 Properties of dual static complex CMOS gates Rail-to-rail excursion: large noise margin João Canas Ferreira (FEUP) CMOS logic gates March / 37

20 Properties of dual static complex CMOS gates Rail-to-rail excursion: large noise margin Logic levels do not depend on the size of the devices (ratioless logic) João Canas Ferreira (FEUP) CMOS logic gates March / 37

21 Properties of dual static complex CMOS gates Rail-to-rail excursion: large noise margin Logic levels do not depend on the size of the devices (ratioless logic) Steady-state path from output to Vdd/Gnd: low output resistance João Canas Ferreira (FEUP) CMOS logic gates March / 37

22 Properties of dual static complex CMOS gates Rail-to-rail excursion: large noise margin Logic levels do not depend on the size of the devices (ratioless logic) Steady-state path from output to Vdd/Gnd: low output resistance Very high input resistance (input DC current 0) João Canas Ferreira (FEUP) CMOS logic gates March / 37

23 Properties of dual static complex CMOS gates Rail-to-rail excursion: large noise margin Logic levels do not depend on the size of the devices (ratioless logic) Steady-state path from output to Vdd/Gnd: low output resistance Very high input resistance (input DC current 0) No direct path between Vdd and Gnd: no static power dissipation João Canas Ferreira (FEUP) CMOS logic gates March / 37

24 Properties of dual static complex CMOS gates Rail-to-rail excursion: large noise margin Logic levels do not depend on the size of the devices (ratioless logic) Steady-state path from output to Vdd/Gnd: low output resistance Very high input resistance (input DC current 0) No direct path between Vdd and Gnd: no static power dissipation Delay depends (mainly) on the load capacitance and the equivalent resistance (R on ) of the transistors. João Canas Ferreira (FEUP) CMOS logic gates March / 37

25 Models for calculating propagation delay Subsritute transistors by switch and R eq Include intrinsic capacitance of internal nodes João Canas Ferreira (FEUP) CMOS logic gates March / 37

26 Delay is dependent on input patterns João Canas Ferreira (FEUP) CMOS logic gates March / 37

27 Delay is dependent on input patterns Delay depends on pull-up/pull-down path João Canas Ferreira (FEUP) CMOS logic gates March / 37

28 Delay is dependent on input patterns Delay depends on pull-up/pull-down path 0 to 1 output transition: João Canas Ferreira (FEUP) CMOS logic gates March / 37

29 Delay is dependent on input patterns Delay depends on pull-up/pull-down path 0 to 1 output transition: both inputs are zero: 0.69 (R p /2)C L João Canas Ferreira (FEUP) CMOS logic gates March / 37

30 Delay is dependent on input patterns Delay depends on pull-up/pull-down path 0 to 1 output transition: both inputs are zero: 0.69 (R p /2)C L one input is zero: 0.69 R p C L João Canas Ferreira (FEUP) CMOS logic gates March / 37

31 Delay is dependent on input patterns Delay depends on pull-up/pull-down path 0 to 1 output transition: both inputs are zero: 0.69 (R p /2)C L one input is zero: 0.69 R p C L 1 to 0 output transition: João Canas Ferreira (FEUP) CMOS logic gates March / 37

32 Delay is dependent on input patterns Delay depends on pull-up/pull-down path 0 to 1 output transition: both inputs are zero: 0.69 (R p /2)C L one input is zero: 0.69 R p C L 1 to 0 output transition: both inputs are 1 : R n C L João Canas Ferreira (FEUP) CMOS logic gates March / 37

33 Delay is dependent on input patterns Delay depends on pull-up/pull-down path 0 to 1 output transition: both inputs are zero: 0.69 (R p /2)C L one input is zero: 0.69 R p C L 1 to 0 output transition: both inputs are 1 : R n C L includingintr (Elmore delay approximation): 0.69 (R n C intr + 2 R n C L ) João Canas Ferreira (FEUP) CMOS logic gates March / 37

34 NND2: input dependent delay NMOS: 0.5 µm/0.25 µm PMOS: 0.75 µm/0.25 µm C L =100 ff Voltage (V) Source: [Rabaey03] time (ps) Input pattern Delay (ps) =B= =1, B= =0 1, B=1 50 =B= =1, B= =1 0, B=1 57 João Canas Ferreira (FEUP) CMOS logic gates March / 37

35 Transistor sizing (1) Symmetric (balanced) gates (assuming β = 2) Size in multiples of (W min /L min ) (multiplying W) João Canas Ferreira (FEUP) CMOS logic gates March / 37

36 Transistor sizing (2) Starting with the left branch Starting with the right branch series of transistors has the equivalent size: For constant L: (W/L) eq = For parallel devices: For constant L: (W/L) 1 + (W/L) W eq = 1 W 1 + W (W/L) eq = (W/L) 1 + (W/L) W eq = W 1 + W João Canas Ferreira (FEUP) CMOS logic gates March / 37

37 Influence of the number of inputs João Canas Ferreira (FEUP) CMOS logic gates March / 37

38 Influence of the number of inputs Elmore estimate of the propagation delay:: t phl = 0.69((R 1 C 1 + (R 1 + R 2 ) C 2 + (R 1 + R 2 + R 3 ) C 3 + (R 1 + R 2 + R 3 + R 4 ) C L ) Equal NMOS transistors: t phl = 0.69 R eqn (C C C C L ) Propagation delay degrades significantly with increasing number of inputs (fan-in); in the worst case, quadratically ( N = N(N 1)/2). João Canas Ferreira (FEUP) CMOS logic gates March / 37

39 Propagation delay as a function of the number of inputs Source: [Rabaey03] Practical rule: void logic gates with more than four inputs. João Canas Ferreira (FEUP) CMOS logic gates March / 37

40 Propagation delay as a function of effective fan-out Effective fan-out: F = C load C input Source: [Rabaey03] João Canas Ferreira (FEUP) CMOS logic gates March / 37

41 Reducing propagation delay (1) Make transistors wider Useful while external load capacitance is dominant. João Canas Ferreira (FEUP) CMOS logic gates March / 37

42 Reducing propagation delay (1) Make transistors wider Useful while external load capacitance is dominant. Progressive sizing M 1 > M 2 > M 3 >... > M N (FET closer to the output is the smallest) May reduce delay by more than 20 % João Canas Ferreira (FEUP) CMOS logic gates March / 37

43 Reducing propagation delay (2) Consider arrival order of signal I 3 1 M 3 C L charged 0 1 I 3 M 3 C L charged I 2 1 M 2 C 2 charged I 2 1 M 2 C 2 uncharged 0 1 I 1 M1 C 1 charged I 1 1 M1 C 1 uncharged delay determined by discharge of C L, C 1 e C 2 delay determined by discharge of C L João Canas Ferreira (FEUP) CMOS logic gates March / 37

44 Reducing propagation delay (3) Chose structure that allow a smaller fan-in Example: F = BCDEFG Question: how to select the fastest structure? João Canas Ferreira (FEUP) CMOS logic gates March / 37

45 Reducing propagation delay (4) Buffer insertion Question: what is the ideal number of buffers and their sizes? João Canas Ferreira (FEUP) CMOS logic gates March / 37

46 Topics 1 General structure 2 General properties 3 Cell layout João Canas Ferreira (FEUP) CMOS logic gates March / 37

47 Standard cell ( 1980 s) Source: [Rabaey03] Contacts and well not shown João Canas Ferreira (FEUP) CMOS logic gates March / 37

48 Standard cell (1990 s) Mirrored cell No channel Mirrored cell Source: [Rabaey03] João Canas Ferreira (FEUP) CMOS logic gates March / 37

49 Structure of a cell (inverter) Height: 12 metal tracks Metal track approx. 3λ + 3λ Pitch: distance between repeated objects Cell height: "12 pitch" cell border Supply ~ 10 λ Source: [Rabaey03] João Canas Ferreira (FEUP) CMOS logic gates March / 37

50 Variants of inverter cell Minimum routing in diffusion Silicidade diffusion Source: [Rabaey03] João Canas Ferreira (FEUP) CMOS logic gates March / 37

51 Two-input NND gate Source: [Rabaey03] João Canas Ferreira (FEUP) CMOS logic gates March / 37

52 Layout planning (stick diagrams) Source: [Rabaey03] No sizes Relative positions João Canas Ferreira (FEUP) CMOS logic gates March / 37

53 Layout planning of complex cells X B Y C X C C Vdd C Z X = C (+B) B B B Z Y Gnd 1 Draw two graphs (one for each network) where the nodes represent circuit nodes and edges represent devices. 2 Find a consistent Euler paths through each graph. Euler path: path through all the edges (just once) Layout with continuous diffusion! The two paths must be consistent : same sequence of nodes on both paths (just one poly line for both nmos and pmos devices). João Canas Ferreira (FEUP) CMOS logic gates March / 37

54 Example: Two implementation alternatives Source: [Rabaey03] Cell on the right: no diffusion breaks João Canas Ferreira (FEUP) CMOS logic gates March / 37

55 nother example: Logic gate OI22 X C D C B D X D C Vdd C X = (+B)(C+D) D B B B Gnd João Canas Ferreira (FEUP) CMOS logic gates March / 37

56 Wide transistors One nger Two ngers Less diffusion capacitance Source: [Rabaey03] João Canas Ferreira (FEUP) CMOS logic gates March / 37

57 References Some of the figures come from the book: Rabaey03 J. M. Rabaey et al, Digital Integrated Circuits, 2nd edition,prentice Hall, João Canas Ferreira (FEUP) CMOS logic gates March / 37

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