EE5311 Digital IC Design


 Betty Hensley
 4 years ago
 Views:
Transcription
1 EE5311 Digital IC Design Module 3  The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 3, 2018 Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 1/37
2 Learning Objectives Explain the functioning of a CMOS inverter Explain the Voltage Transfer Characteristics of an inverter Derive an expression for the trip point of an inverter Derive an expression for the delay of an inverter driving a load Derive expressions for Static, Dynamic and Short Circuit power of an inverter. Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 2/37
3 Outline Switch Model Transfer Characteristics Switching Threshold Noise Margin Supply Voltage Scaling Propagation Delay Power Dynamic Short circuit Leakage Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 3/37
4 Inverters  Robust Configuration V DD 0 V DD V Tp V DD V DD 0 V DD V Tn 0 V DD Pull down to GND with NMOS Pull up to V DD with PMOS Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 4/37
5 Load Line V in G S D Vout D S Figure: The CMOS Inverter I DSp = I DSn V GSn = V in V GSp = V in V DD V DSn = V out V DSp = V out V DD Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 5/37
6 Load Line I Dn V in = 0 V in = 0.4V DD V in = V DD V in = 0.7V DD V in = 0.5V DD V in = 0.7V DD V in = 0.4V DD V in = V DD V in = 0 V out Figure: Solid lines NMOS, Dashed lines  PMOS Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 6/37
7 Voltage Transfer Characterisitcs V out V in V out V in = V Out = V M C L V in Figure: VTC of a CMOS Inverter Region NMOS PMOS 1 Off Lin 2 Sat Lin 3 Sat Sat 4 Lin Sat 5 Lin Off Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 7/37
8 Switching Threshold V out V in V out V in = V Out = C L V in Figure: Switching Threshold Both NMOS and PMOS are in saturation Assume velocity saturation Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 8/37
9 Switching Threshold I DSp = I DSn V GSn = V in V GSp = V in V DD V DSn = V out V DSp = V out V DD V in = V out Both NMOS and PMOS are in saturation Assume velocity saturation Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 9/37
10 Switching Threshold Ignoring channel length modulation I DSn = k n W n L (V M V Tn V DSATn 2 I DSp = k p W p L (V M V DD V Tp V DSATp 2 )V DSATn )V DSATp V M = V Tn + V DSATn 2 +r(v DD +V Tp + V DSATp 2 ) 1+r r = k p(w p /L)V DSATp k n(w n /L)V DSATn = W pv satp W n v satn V M r r +1 V DD Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 10/37
11 Switing Threshold V out V in = V Out = V M Increasing r Figure: VTC Trip Point V in Ratio of Wp W n determines V M Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 11/37
12 Switing Threshold Without Velocity Saturation Left as an exercise V M = V Tn +r(v DD +V Tp ) 1+r kp r = k n Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 12/37
13 Noise Margin V out V OH V OL V IL V IH Vin V OH V OL NM H NM L V IH V IL Figure: Noise Margin of a CMOS Inverter Logic levels from the driver should be recognized by the load Points of slope 1 provide the noise margin levels NM H = V OH V IH NM L = V IL V OL Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 13/37
14 Noise Margin Approximation V out V M V IL V IH V in Figure: Noise Margin approximation of a CMOS Inverter Extend the tangent at V M Slope is the gain (g) of the VTC NM H = V DD V IH = V DD V M + V M g NM L = V IL = V M + V DD V M g Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 14/37
15 Noise Margin Calculations Need to consider channel length modulation Slope is the gain (g = dvout dv in ) of the VTC I DSn = I no clm DSn (1+λ n V out ) I DSp = I no clm DSp (1+λ p (V out V DD )) g = 1 k n V DSATn +k p V DSATp I D (V M ) λ n λ p 1+r g (V M V Tn V DSATn /2)(λ n λ p ) r = k pv DSATp k n V DSATn Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 15/37
16 Pass Transistors V D v C (0 ) = 0 V D V G v C (0 ) = V DD V G v C (t) = min(v G V Tn,V D ) v C (t) = max(v G V Tp,V D ) Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 16/37
17 Switch Model V in = 0 V in = V DD Vin V out R p R n C L Figure: The CMOS Inverter The high and low logic levels are V DD and GND(0) Logic levels are independent of sizes  Ratioless Logic Low output impedance (kω)  Immune to noise Large input impedance  Infinite fanout No conduction path from supply to ground in steady state Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 17/37
18 Switch Model Dynamic Behaviour V in 0 V in V DD R p C L R n C L Low High High Low Figure: Dynamic Behaviour of CMOS Inverter τ rise = R p C L τ fall = R n C L Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 18/37
19 Delay Propagation Delay  50% input to 50% output Rise delay. Output goes from L H  tplh Fall delay. Output goes from H L  tphl Propagation delay is defined as tp = t phl+t plh 2 Slew Rise time  Time taken for output to go from 10% to 90% Fall time  TIme taken for output to go from 90% to 10% Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 19/37
20 Delay V in V out V in V out C L t phl t plh t Figure: Delay t phl = R eqn C L t plh = R eqp C L t p = C L R eqn +R eqp 2 Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 20/37
21 Transistor Sizing  Symmetric delay Rising propagation delay should be identical to falling propagation delay. This also ensures a symmeteric VTC t phl = t plh R eqn = R eqp C L V DD 2I DSATn = C LV DD 2I DSATp W n µ n = W p µ p W p 2W n Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 21/37
22 Transistor Sizing  Minimum delay C L = C dp1 +C dn1 +C gn2 +C gp2 +C wire t p = C L R eqn +R eqp 2 t p = (0.5)[(1+β)(C gn2 +C dn1 )+C wire ]R eqn (1+ α β ) α = R p = W n ;β = W p R eqn W n t p β = 0 ( ) C wire β opt = α 1+ C dn1 +C gn2 Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 22/37
23 Power Dissipation Energy lost as heat disspation in the devices Dynamic  Charge/ Discharging of cpacitance Short Circuit  Conductive path from V DD GND Static  Leakage even when no activity happens Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 23/37
24 Dynamic Power V in 0 V in V DD R p C L R n C L Low High High Low Figure: Capacitor charge and discharge E VDD = E C = 0 0 L H i VDD (t)v DD dt i VDD (t)v out dt Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 24/37
25 Dynamic Power E VDD = E VDD = E VDD = 0 0 VDD 0 L H i VDD (t)v DD dt dv out C L V DD dt dt C L V DD dv out E VDD = C L V 2 DD E C = C LV 2 DD 2 Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 25/37
26 Dynamic Power L H  Load capacitor charges and disspates C LV 2 DD 2 in PMOS H L  Load capacitor discharges and disspates C LV 2 DD 2 in NMOS Note that the energy dissipated is independent of size Depends on Probability of switching (P0 1 )  Activity factor Frequency of operation (f) P dyn = C L V 2 DDf 0 1 P dyn = C L V 2 DDP 0 1 f Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 26/37
27 Short Circuit Power V DD V T V in I sc V out V T I peak C L Figure: Both NMOS and PMOS conduct I peak t sc I Peak t sc E sc = V DD +V DD 2 2 P sc = t sc V DD I peak f t sc = V DD +V Tp V Tn t s V DD Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 27/37
28 Static Power 0 ON V DD V DD 0 ON I subn I subp Figure: NMOS or PMOS leaks current P stat = I stat V DD P tot = P dyn +P sc +P stat P tot = (C L V 2 DD +V DD I peak t s )f 0 1 +V DD I leak Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 28/37
29 Stacking Effect The intermedaite node : 0 < V X < V DD Exponentially reduces the leakage of the series stack (I 2 << I 1 ) Increase in V TH of the top transistor due to body effect 0 VDD 0 I1 VGS = VX,VSB = VX 0 0 VDD 0 VX I2 VGS = 0 ITOP e ( VX VTn)/nφt IBOT e ( VTn)/nφt IBOT = ITOP Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 29/37
30 Process Variations Impossible to manufacture tiny dimensions accurately Variations are not avoidable Process Parameters : T OX, N A, L e x j, µ n,µ p see variations Performance Parameters: Currents and Voltages Process variation information (µ, σ) are provided to designers Performance parameter variation in simulation should match measured variations Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 30/37
31 Process Variations I MEAS D,1 L e MANUFACTURING I MEAS D,3 I MEAS D,2 N A WAFER : 200mm (8 in) or 300mm (12 in) SIMULATION I SIM D SHOULD MATCH Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 31/37
32 Global Variations DIFFERENT CHIP 1 I MEAS D,1 CHIP 2 I MEAS D,2 I MEAS D,1 I MEAS D,2 SAME WAFER : 200mm (8 in) or 300mm (12 in) All transistors within a chip affected in the same way Transistors in different chips across the wafer affected differently Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 32/37
33 Global Variations FAST N CHIP 1 IDN,1 MEAS SLOW P IDP,1 MEAS SLOW N CHIP 2 IDN,2 MEAS FAST P IDP,2 MEAS WAFER : 200mm (8 in) or 300mm (12 in) Manufacturing process of (N and P)MOS are different Transistors end up being Fast (F), Slow (S) or Typical (T) All N can get biased in one direction All P can get biased in another Corner simulation (N,P) : (TT, FS, FF, SF, SS) Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 33/37
34 Local Variations Transistors sitting right next to each other will be different Happens mainly due to Random Dopant Fluctuation Large transistors are affect lesser than small ones (σ Local 1 LW ) Requires large number of statistical simulations to ensure correct functionality Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 34/37
35 Ring Oscillators Excellent process monitors Good representative of all digital circuits Can be added by the FAB in Kerf regions or by designers in their chip Measure the frequency of oscilations to determine the global process corner Can be added in multiple corners of a large chip to measure any across chip variation 2N +1 Inverters T P Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 35/37
36 Ring Oscillators 2N +1 Inverters EN T P T P 2x(2N +1)τ inv EN = 0 prevents any oscillations  Saves dynamic power Usually a couple of 100 INV long Very high frequency of oscillations Divided several times before being brought out of the chip Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 36/37
37 References The material presented here is based on the following books/ lecture notes 1. Digital Integrated Circuits Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic 2nd Edition, Prentice Hall India Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 37/37
EE5311 Digital IC Design
EE5311 Digital IC Design Module 3  The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 6, 2017 Janakiraman, IITM
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br
More informationENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)
ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 14 The CMOS Inverter: dynamic behavior (sizing, inverter
More informationEEE 421 VLSI Circuits
EEE 421 CMOS Properties Full railtorail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady
More informationECE 342 Solid State Devices & Circuits 4. CMOS
ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More information5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1
5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design
More informationVLSI Design and Simulation
VLSI Design and Simulation CMOS Inverters Topics Inverter VTC Noise Margin Static Load Inverters CMOS Inverter FirstOrder DC Analysis R p V OL = 0 V OH = R n =0 = CMOS Inverter: Transient Response R p
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD V in V out C L CMOS Properties Full railtorail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power
More informationChapter 5. The Inverter. V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov Inverter
Chapter 5 The Inverter V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov.12 03 Objective of This Chapter Use Inverter to know basic CMOS Circuits Operations Watch for performance Index such as Speed (Delay calculation)
More informationDigital Integrated Circuits 2nd Inverter
Digital Integrated Circuits The Inverter The CMOS Inverter V DD Analysis Inverter complex gate Cost V in V out complexity & Area Integrity and robustness C L Static behavior Performance Dynamic response
More informationECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model
ECE 34 Electronic Circuits Lecture 35 CMOS Delay Model Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More information2007 Fall: Electronic Circuits 2 CHAPTER 10. DeogKyoon Jeong School of Electrical Engineering
007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits DeogKyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we
More informationLecture 4: CMOS review & Dynamic Logic
Lecture 4: CMOS review & Dynamic Logic Reading: ch5, ch6 Overview CMOS basics Power and energy in CMOS Dynamic logic 1 CMOS Properties Full railtorail swing high noise margins Logic levels not dependent
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor NChannel MOSFET Built on ptype
More informationEE115C Digital Electronic Circuits Homework #3
Electrical Engineering Department Spring 1 EE115C Digital Electronic Circuits Homework #3 Due Thursday, April, 6pm @ 56147E EIV Solution Problem 1 VTC and Inverter Analysis Figure 1a shows a standard
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler
More informationLecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:308:00pm in 105 Northgate
EE4Fall 2008 Digital Integrated Circuits Lecture VTCs and Delay Lecture # Announcements No lab today, Mon., Tues. Labs restart next week Midterm # Tues. Oct. 7 th, 6:308:00pm in 05 Northgate Exam is
More informationDC and Transient Responses (i.e. delay) (some comments on power too!)
DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02  CMOS Transistor Theory & the Effects of Scaling
More informationDigital Microelectronic Circuits ( ) The CMOS Inverter. Lecture 4: Presented by: Adam Teman
Digital Microelectronic Circuits (3611301 ) Presented by: Adam Teman Lecture 4: The CMOS Inverter 1 Last Lectures Moore s Law Terminology» Static Properties» Dynamic Properties» Power The MOSFET Transistor»
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationLecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More informationMidterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!
More informationEE5780 Advanced VLSI CAD
EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay
More informationEE5311 Digital IC Design
EE5311 Digital IC Design Module 1  The Transistor Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai October 28, 2017 Janakiraman, IITM
More informationDigital Integrated Circuits
Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Shortcircuit current The CMOS inverter :
More informationLecture 14  Digital Circuits (III) CMOS. April 1, 2003
6.12  Microelectronic Devices and Circuits  Spring 23 Lecture 141 Lecture 14  Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:
More informationThe Inverter. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Inverter Revised from Digital Integrated Circuits, Jan M. Rabaey el, 2003 Propagation Delay CMOS
More informationCHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS
CHAPTER 5 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 5. CMOS Logic Gate Circuits 5. Digital Logic Inverters 5.3 The CMOS Inverter 5.4 Dynamic Operation of the CMOS Inverter 5.5 Transistor Sizing 5.6 Power
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationDynamic operation 20
Dynamic operation 20 A simple model for the propagation delay Symmetric inverter (rise and fall delays are identical) otal capacitance is linear t p Minimum length devices R W C L t = 0.69R C = p W L 0.69
More informationMOSFET and CMOS Gate. Copy Right by Wentai Liu
MOSFET and CMOS Gate CMOS Inverter DC Analysis  Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max
More informationThe Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two
More informationLecture 12 Circuits numériques (II)
Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More informationECE321 Electronics I
ECE31 Electronics Lecture 1: CMOS nverter: Noise Margin & Delay Model Payman ZarkeshHa Office: ECE Bldg. 30B Office hours: Tuesday :003:00PM or by appointment Email: payman@ece.unm.edu Slide: 1 CMOS
More informationLecture 4: DC & Transient Response
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide
More informationAnnouncements. EE141 Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power
 Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 123pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances
More informationLecture 6: DC & Transient Response
Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins
More informationTopic 4. The CMOS Inverter
Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ Email: p.cheung@ic.ac.uk Topic 41 Noise in Digital Integrated
More informationEEC 118 Lecture #16: Manufacturability. Rajeevan Amirtharajah University of California, Davis
EEC 118 Lecture #16: Manufacturability Rajeevan Amirtharajah University of California, Davis Outline Finish interconnect discussion Manufacturability: Rabaey G, H (Kang & Leblebici, 14) Amirtharajah, EEC
More information4.10 The CMOS Digital Logic Inverter
11/11/2004 section 4_10 The CMOS Digital Inverter blank.doc 1/1 4.10 The CMOS Digital Logic Inverter Reading Assignment: pp. 336346 Complementary MOSFET (CMOS) is the predominant technology for constructing
More informationDigital Integrated Circuits A Design Perspective
igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational
More information9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 10: February 15, 2018 MOS Inverter: Dynamic Characteristics Penn ESE 570 Spring 2018 Khanna Lecture Outline! Inverter Power! Dynamic Characteristics
More informationCMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 2 Quality Metrics of Digital Design guntzel@inf.ufsc.br
More informationDC & Transient Responses
ECEN454 Digital Integrated Circuit Design DC & Transient Responses ECEN 454 DC Response DC Response: vs. for a gate Ex: Inverter When = > = When = > = In between, depends on transistor size and current
More informationDC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.
DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575604 yrpeng@uark.edu Pass Transistors We have assumed source is
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: CMOS Inverter: Visual VTC. Review: CMOS Inverter: Visual VTC
ESE 570: Digital Integrated Circuits and LSI Fundamentals Lec 0: February 4, 207 MOS Inverter: Dynamic Characteristics Lecture Outline! Review: Symmetric CMOS Inverter Design! Inverter Power! Dynamic Characteristics
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NORgate C = NOT (A or B)
1 Introduction to TransistorLevel Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationCOMP 103. Lecture 16. Dynamic Logic
COMP 03 Lecture 6 Dynamic Logic Reading: 6.3, 6.4 [ll lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP03
More informationCPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look
CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates epartment of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka )
More informationPower Dissipation. Where Does Power Go in CMOS?
Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 16 CMOS Combinational Circuits  2 guntzel@inf.ufsc.br
More informationCOMP 103. Lecture 10. Inverter Dynamics: The Quest for Performance. Section 5.4.2, What is this lecture+ about? PERFORMANCE
COMP 103 Lecture 10 Inverter Dynamics: The Quest for Performance Section 5.4.2, 5.4.3 [All lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 10: February 16, 2016 MOS Inverter: Dynamic Characteristics Lecture Outline! Review: Symmetric CMOS Inverter Design! Inverter Power! Dynamic
More informationCheck course home page periodically for announcements. Homework 2 is due TODAY by 5pm In 240 Cory
EE141 Fall 005 Lecture 6 MOS Capacitances, Propagation elay Important! Check course home page periodically for announcements Homework is due TOAY by 5pm In 40 Cory Homework 3 will be posted TOAY ue Thursday
More informationCMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties.
CMOS Inverter: Steady State Response CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates R p V OL = V OH = V M = f(r n, R p ) epartment of Electrical and Computer Engineering University
More informationEECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 111:3 Thursday, October 6, 6:38:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
More informationEEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 8 Lecture #5: CMOS Inverter AC Characteristics Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Acknowledgments Slides due to Rajit Manohar from ECE 547 Advanced
More informationCMOS Technology for Computer Architects
CMOS Technology for Computer Architects Recap Technology Trends Lecture 2: Transistor Inverter Iakovos Mavroidis Giorgos Passas Manolis Katevenis FORTHICS (University of Crete) 1 2 Recap Threshold Voltage
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 13 The CMOS Inverter: dynamic behavior (delay) guntzel@inf.ufsc.br
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationLecture 13  Digital Circuits (II) MOS Inverter Circuits. March 20, 2003
6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 131 Lecture 13 Digital Circuits (II) MOS Inverter Circuits March 20, 2003 Contents: 1. NMOS inverter with resistor pullup (cont.) 2. NMOS
More informationMiscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]
Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an NSwitch, the
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models MOS
More informationHightoLow Propagation Delay t PHL
HightoLow Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (nchannel) immediately switches from cutoff to saturation; the pchannel pullup switches from triode to
More informationCMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic [dapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey,. Chandrakasan,. Nikolic] Sp11 CMPEN 411
More informationWhere Does Power Go in CMOS?
Power Dissipation Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking
More informationEE115C Digital Electronic Circuits Homework #4
EE115 Digital Electronic ircuits Homework #4 Problem 1 Power Dissipation Solution Vdd =1.0V onsider the source follower circuit used to drive a load L =20fF shown above. M1 and M2 are both NMOS transistors
More informationDigital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo
Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Dynamic Logic Introduction Digital IC EE141 2 Dynamic logic outline Dynamic logic principle Dynamic logic
More informationLast Lecture. Power Dissipation CMOS Scaling. EECS 141 S02 Lecture 8
EECS 141 S02 Lecture 8 Power Dissipation CMOS Scaling Last Lecture CMOS Inverter loading Switching Performance Evaluation Design optimization Inverter Sizing 1 Today CMOS Inverter power dissipation» Dynamic»
More informationB.Supmonchai July 5th, q Quantification of Design Metrics of an inverter. q Optimization of an inverter design. B.Supmonchai Why CMOS Inverter?
July 5th, 4 Goals of This Chapter Quantification of Design Metrics of an inverter Static (or SteadyState) Behavior Chapter 5 CMOS Inverter Boonchuay Supmonchai Integrated Design Application Research (IDAR)
More informationBased on slides/material by. Topic 34. Combinational Logic. Outline. The CMOS Inverter: A First Glance
ased on slides/material by Topic 3 J. Rabaey http://bwrc.eecs.berkeley.edu/lasses/icook/instructors.html Digital Integrated ircuits: Design Perspective, Prentice Hall D. Harris http://www.cmosvlsi.com/coursematerials.html
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 17: March 26, 2019 Energy Optimization & Design Space Exploration Penn ESE 570 Spring 2019 Khanna Lecture Outline! Energy Optimization! Design
More information5. CMOS Gate Characteristics CS755
5. CMOS Gate Characteristics Last module: CMOS Transistor theory This module: DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Transistor ehavior 1) If the width of a transistor
More informationTHE CMOS INVERTER CHAPTER. Quantification of integrity, performance, and energy metrics of an inverter Optimization of an inverter design
chapter5.fm Page 176 Friday, January 18, 2002 9:01 M CHPTER 5 THE CMOS INVERTER Quantification of integrity, performance, and energy metrics of an inverter Optimization of an inverter design 5.1 Introduction
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Introduction Digital IC Dynamic Logic Introduction Digital IC 2 EE141 Dynamic
More informationCMOS Logic Gates. University of Connecticut 181
CMOS Logic Gates University of Connecticut 181 Basic CMOS Inverter Operation V IN P O N O pchannel enhancementtype MOSFET; V T < 0 nchannel enhancementtype MOSFET; V T > 0 If V IN 0, N O is cut off and
More informationEE40 Lec 20. MOS Circuits
EE40 Lec 20 MOS Circuits eading: Chap. 12 of Hambley Supplement reading on MOS Circuits http://www.inst.eecs.berkeley.edu/~ee40/fa09/handouts/ee40_mos_circuit.pdf Slide 1 Bias circuits OUTLINE Smallsignal
More informationESE 570 MOS INVERTERS STATIC (DC Steady State) CHARACTERISTICS. Kenneth R. Laker, University of Pennsylvania, updated 12Feb15
ESE 570 MOS INVERTERS STATIC (DC Steady State) CHARACTERISTICS 1 VDD Vout Vin Ideal VTC Logic 0 = 0 V Logic 1 = VDD 0 2 VOH VDD VOL 0 o.c. Cout For DC steadystate Cout is open circuit. VDD 0 VDD VOL VT0n
More informationCOMBINATIONAL LOGIC. Combinational Logic
COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino npcmos Combinational vs. Sequential Logic In Logic
More informationLecture 81. Low Power Design
Lecture 8 Konstantinos Masselos Department of Electrical & Electronic Engineering Imperial College London URL: http://cas.ee.ic.ac.uk/~kostas Email: k.masselos@ic.ac.uk Lecture 81 Based on slides/material
More informationProperties of CMOS Gates Snapshot
MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)
More informationAnnouncements. EE141 Spring 2003 Lecture 8. Power Inverter Chain
 Spring 2003 Lecture 8 Power Inverter Chain Announcements Homework 3 due today. Homework 4 will be posted later today. Special office hours from :303pm at BWRC (in lieu of Tuesday) Today s lecture Power
More informationEECS 427 Lecture 11: Power and Energy Reading: EECS 427 F09 Lecture Reminders
EECS 47 Lecture 11: Power and Energy Reading: 5.55 [Adapted from Irwin and Narayanan] 1 Reminders CAD5 is due Wednesday 10/8 You can submit it by Thursday 10/9 at noon Lecture on 11/ will be taught by
More informationEE115C Winter 2017 Digital Electronic Circuits. Lecture 6: Power Consumption
EE115C Winter 2017 Digital Electronic Circuits Lecture 6: Power Consumption Four Key Design Metrics for Digital ICs Cost of ICs Reliability Speed Power EE115C Winter 2017 2 Power and Energy Challenges
More informationΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018
ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018 ΔΙΑΛΕΞΗ 11: Dynamic CMOS Circuits ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ (ttheocharides@ucy.ac.cy) (ack: Prof. Mary Jane Irwin and Vijay Narayanan) [Προσαρμογή από
More informationENEE 359a Digital VLSI Design
SLIDE 1 ENEE 359a Digital VLSI Design & Logical Effort Prof. blj@ece.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay
More informationEEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW
More informationUsing MOS Models. C.K. Ken Yang UCLA Courtesy of MAH EE 215B
Using MOS Models C.K. Ken Yang UCLA yangck@ucla.edu Courtesy of MAH 1 Overview Reading Rabaey 5.4 W&H 4.2 Background In the past two lectures we have reviewed the iv and CV curves for MOS devices, both
More informationDigital Integrated Circuits A Design Perspective
Designing ombinational Logic ircuits dapted from hapter 6 of Digital Integrated ircuits Design Perspective Jan M. Rabaey et al. opyright 2003 Prentice Hall/Pearson 1 ombinational vs. Sequential Logic In
More informationIntegrated Circuit Design ELCT 701 (Winter 2017) Lecture 2: Resistive Load Inverter
1 Integrated Circuit Design ELCT 701 (Winter 017) Lecture : Resistive Load Inverter Assistant Professor Office: C3.315 Email: eman.azab@guc.edu.eg Digital Inverters Introduction 3 Digital Inverter: Introduction
More information