EE5311 Digital IC Design


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1 EE5311 Digital IC Design Module 3  The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 3, 2018 Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 1/37
2 Learning Objectives Explain the functioning of a CMOS inverter Explain the Voltage Transfer Characteristics of an inverter Derive an expression for the trip point of an inverter Derive an expression for the delay of an inverter driving a load Derive expressions for Static, Dynamic and Short Circuit power of an inverter. Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 2/37
3 Outline Switch Model Transfer Characteristics Switching Threshold Noise Margin Supply Voltage Scaling Propagation Delay Power Dynamic Short circuit Leakage Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 3/37
4 Inverters  Robust Configuration V DD 0 V DD V Tp V DD V DD 0 V DD V Tn 0 V DD Pull down to GND with NMOS Pull up to V DD with PMOS Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 4/37
5 Load Line V in G S D Vout D S Figure: The CMOS Inverter I DSp = I DSn V GSn = V in V GSp = V in V DD V DSn = V out V DSp = V out V DD Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 5/37
6 Load Line I Dn V in = 0 V in = 0.4V DD V in = V DD V in = 0.7V DD V in = 0.5V DD V in = 0.7V DD V in = 0.4V DD V in = V DD V in = 0 V out Figure: Solid lines NMOS, Dashed lines  PMOS Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 6/37
7 Voltage Transfer Characterisitcs V out V in V out V in = V Out = V M C L V in Figure: VTC of a CMOS Inverter Region NMOS PMOS 1 Off Lin 2 Sat Lin 3 Sat Sat 4 Lin Sat 5 Lin Off Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 7/37
8 Switching Threshold V out V in V out V in = V Out = C L V in Figure: Switching Threshold Both NMOS and PMOS are in saturation Assume velocity saturation Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 8/37
9 Switching Threshold I DSp = I DSn V GSn = V in V GSp = V in V DD V DSn = V out V DSp = V out V DD V in = V out Both NMOS and PMOS are in saturation Assume velocity saturation Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 9/37
10 Switching Threshold Ignoring channel length modulation I DSn = k n W n L (V M V Tn V DSATn 2 I DSp = k p W p L (V M V DD V Tp V DSATp 2 )V DSATn )V DSATp V M = V Tn + V DSATn 2 +r(v DD +V Tp + V DSATp 2 ) 1+r r = k p(w p /L)V DSATp k n(w n /L)V DSATn = W pv satp W n v satn V M r r +1 V DD Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 10/37
11 Switing Threshold V out V in = V Out = V M Increasing r Figure: VTC Trip Point V in Ratio of Wp W n determines V M Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 11/37
12 Switing Threshold Without Velocity Saturation Left as an exercise V M = V Tn +r(v DD +V Tp ) 1+r kp r = k n Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 12/37
13 Noise Margin V out V OH V OL V IL V IH Vin V OH V OL NM H NM L V IH V IL Figure: Noise Margin of a CMOS Inverter Logic levels from the driver should be recognized by the load Points of slope 1 provide the noise margin levels NM H = V OH V IH NM L = V IL V OL Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 13/37
14 Noise Margin Approximation V out V M V IL V IH V in Figure: Noise Margin approximation of a CMOS Inverter Extend the tangent at V M Slope is the gain (g) of the VTC NM H = V DD V IH = V DD V M + V M g NM L = V IL = V M + V DD V M g Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 14/37
15 Noise Margin Calculations Need to consider channel length modulation Slope is the gain (g = dvout dv in ) of the VTC I DSn = I no clm DSn (1+λ n V out ) I DSp = I no clm DSp (1+λ p (V out V DD )) g = 1 k n V DSATn +k p V DSATp I D (V M ) λ n λ p 1+r g (V M V Tn V DSATn /2)(λ n λ p ) r = k pv DSATp k n V DSATn Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 15/37
16 Pass Transistors V D v C (0 ) = 0 V D V G v C (0 ) = V DD V G v C (t) = min(v G V Tn,V D ) v C (t) = max(v G V Tp,V D ) Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 16/37
17 Switch Model V in = 0 V in = V DD Vin V out R p R n C L Figure: The CMOS Inverter The high and low logic levels are V DD and GND(0) Logic levels are independent of sizes  Ratioless Logic Low output impedance (kω)  Immune to noise Large input impedance  Infinite fanout No conduction path from supply to ground in steady state Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 17/37
18 Switch Model Dynamic Behaviour V in 0 V in V DD R p C L R n C L Low High High Low Figure: Dynamic Behaviour of CMOS Inverter τ rise = R p C L τ fall = R n C L Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 18/37
19 Delay Propagation Delay  50% input to 50% output Rise delay. Output goes from L H  tplh Fall delay. Output goes from H L  tphl Propagation delay is defined as tp = t phl+t plh 2 Slew Rise time  Time taken for output to go from 10% to 90% Fall time  TIme taken for output to go from 90% to 10% Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 19/37
20 Delay V in V out V in V out C L t phl t plh t Figure: Delay t phl = R eqn C L t plh = R eqp C L t p = C L R eqn +R eqp 2 Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 20/37
21 Transistor Sizing  Symmetric delay Rising propagation delay should be identical to falling propagation delay. This also ensures a symmeteric VTC t phl = t plh R eqn = R eqp C L V DD 2I DSATn = C LV DD 2I DSATp W n µ n = W p µ p W p 2W n Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 21/37
22 Transistor Sizing  Minimum delay C L = C dp1 +C dn1 +C gn2 +C gp2 +C wire t p = C L R eqn +R eqp 2 t p = (0.5)[(1+β)(C gn2 +C dn1 )+C wire ]R eqn (1+ α β ) α = R p = W n ;β = W p R eqn W n t p β = 0 ( ) C wire β opt = α 1+ C dn1 +C gn2 Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 22/37
23 Power Dissipation Energy lost as heat disspation in the devices Dynamic  Charge/ Discharging of cpacitance Short Circuit  Conductive path from V DD GND Static  Leakage even when no activity happens Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 23/37
24 Dynamic Power V in 0 V in V DD R p C L R n C L Low High High Low Figure: Capacitor charge and discharge E VDD = E C = 0 0 L H i VDD (t)v DD dt i VDD (t)v out dt Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 24/37
25 Dynamic Power E VDD = E VDD = E VDD = 0 0 VDD 0 L H i VDD (t)v DD dt dv out C L V DD dt dt C L V DD dv out E VDD = C L V 2 DD E C = C LV 2 DD 2 Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 25/37
26 Dynamic Power L H  Load capacitor charges and disspates C LV 2 DD 2 in PMOS H L  Load capacitor discharges and disspates C LV 2 DD 2 in NMOS Note that the energy dissipated is independent of size Depends on Probability of switching (P0 1 )  Activity factor Frequency of operation (f) P dyn = C L V 2 DDf 0 1 P dyn = C L V 2 DDP 0 1 f Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 26/37
27 Short Circuit Power V DD V T V in I sc V out V T I peak C L Figure: Both NMOS and PMOS conduct I peak t sc I Peak t sc E sc = V DD +V DD 2 2 P sc = t sc V DD I peak f t sc = V DD +V Tp V Tn t s V DD Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 27/37
28 Static Power 0 ON V DD V DD 0 ON I subn I subp Figure: NMOS or PMOS leaks current P stat = I stat V DD P tot = P dyn +P sc +P stat P tot = (C L V 2 DD +V DD I peak t s )f 0 1 +V DD I leak Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 28/37
29 Stacking Effect The intermedaite node : 0 < V X < V DD Exponentially reduces the leakage of the series stack (I 2 << I 1 ) Increase in V TH of the top transistor due to body effect 0 VDD 0 I1 VGS = VX,VSB = VX 0 0 VDD 0 VX I2 VGS = 0 ITOP e ( VX VTn)/nφt IBOT e ( VTn)/nφt IBOT = ITOP Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 29/37
30 Process Variations Impossible to manufacture tiny dimensions accurately Variations are not avoidable Process Parameters : T OX, N A, L e x j, µ n,µ p see variations Performance Parameters: Currents and Voltages Process variation information (µ, σ) are provided to designers Performance parameter variation in simulation should match measured variations Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 30/37
31 Process Variations I MEAS D,1 L e MANUFACTURING I MEAS D,3 I MEAS D,2 N A WAFER : 200mm (8 in) or 300mm (12 in) SIMULATION I SIM D SHOULD MATCH Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 31/37
32 Global Variations DIFFERENT CHIP 1 I MEAS D,1 CHIP 2 I MEAS D,2 I MEAS D,1 I MEAS D,2 SAME WAFER : 200mm (8 in) or 300mm (12 in) All transistors within a chip affected in the same way Transistors in different chips across the wafer affected differently Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 32/37
33 Global Variations FAST N CHIP 1 IDN,1 MEAS SLOW P IDP,1 MEAS SLOW N CHIP 2 IDN,2 MEAS FAST P IDP,2 MEAS WAFER : 200mm (8 in) or 300mm (12 in) Manufacturing process of (N and P)MOS are different Transistors end up being Fast (F), Slow (S) or Typical (T) All N can get biased in one direction All P can get biased in another Corner simulation (N,P) : (TT, FS, FF, SF, SS) Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 33/37
34 Local Variations Transistors sitting right next to each other will be different Happens mainly due to Random Dopant Fluctuation Large transistors are affect lesser than small ones (σ Local 1 LW ) Requires large number of statistical simulations to ensure correct functionality Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 34/37
35 Ring Oscillators Excellent process monitors Good representative of all digital circuits Can be added by the FAB in Kerf regions or by designers in their chip Measure the frequency of oscilations to determine the global process corner Can be added in multiple corners of a large chip to measure any across chip variation 2N +1 Inverters T P Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 35/37
36 Ring Oscillators 2N +1 Inverters EN T P T P 2x(2N +1)τ inv EN = 0 prevents any oscillations  Saves dynamic power Usually a couple of 100 INV long Very high frequency of oscillations Divided several times before being brought out of the chip Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 36/37
37 References The material presented here is based on the following books/ lecture notes 1. Digital Integrated Circuits Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic 2nd Edition, Prentice Hall India Janakiraman, IITM EE5311 Digital IC Design, Module 3  The Inverter 37/37
EE5311 Digital IC Design
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