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1 EE141 Fall 005 Lecture 6 MOS Capacitances, Propagation elay Important! Check course home page periodically for announcements Homework is due TOAY by 5pm In 40 Cory Homework 3 will be posted TOAY ue Thursday Sep by 5pm EE141
2 Today s Lecture The MOS transistor characteristics for transient analysis Propagation delay EE141 3 Review MOS Transistor Model CMOS Inverter VTC EE141 4
3 Important to Remember! 4 x 10.5 V S = V SAT I (A) 1.5 Linear Velocity Saturation Linear Relationship V = V SAT GT V S = V GT Saturation V S (V) Quadratic Relationship EE141 5 A Unified Model for Manual Analysis define V GT = V GS V T G for V GT 0: I =0 S B I for V GT 0: I W V min = k' VGT V L min λ ( 1+ V ) S with V min = min (V GT, V S, V SAT ) EE141 6
4 PMOS Load Lines Coordinate transform: I p (V Sp ) I n ( ) V in = V + V GSp I n = I p = V + V Sp I n I p V in = 0 I n I n V in= 0 V in = 1.5 V in = 1.5 V GSp = 1 V Sp V Sp V GSp = .5 V in = V + V GSp I n = I p = V + V Sp EE141 7 CMOS Inverter Load Characteristics I n V in = 0 V in =.5 PMOS V in = 0.5 V in = NMOS V in = 1.5 V in = 1 V in = 1.5 V in = 1 V in = V in = 1.5 V in = 1 V in = 0.5 V in =.5 V in = 0 EE141 8
5 CMOS Inverter VTC.5 NMOS off PMOS res NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat NMOS res PMOS off V in EE141 9 Inverter Gain 0  gain g = I ( V g ( V M M V kn VSATn + k p V ) λ λ Tn 1+ r V SATn n p SATp ) ( λ λ ) n p V (V) in EE141 10
6 Gain as a function of V (V) V (V) in V in (V) (V) Gain = V (V) in V in (V) EE Impact of Process Variations.5 (V) Good NMOS Bad PMOS Nominal Good PMOS Bad NMOS Good means: t ox L W V th V in (V) EE141 1
7 Outline ynamic Operation of MOS Transistor MOS Capacitances Propagation elay EE MOS Capacitances G C GS C G S C SB C GB C B B EE141 14
8 The Gate Capacitance Polysilicon gate Source n + x d x d W rain n + L d Top view Gatebulk overlap C gate ε = t ox ox WL Gate oxide t ox n + L n + Cross section EE Gate Capacitance G G G S C GC C GC C GC S S Cutoff Resistive Saturation C GCB C GCS C GC Textbook: page 109 Most important regions in digital design: saturation and cutoff EE141 16
9 G a t e C a p a c i t a n c e ( F ) Gate Capacitance C GC WLC ox WLC ox C GC WLC ox C GCB C GCS =C GC WLC ox C GCS C GC WLC ox 3 V GS 0 1 V S /(V GS V T ) C gate as a function of V GS (with V S = 0) C gate as a function of the degree of saturation EE Measuring the Gate Cap I V GS Capacitance (F) 10 x V GS (V) EE141 18
10 iffusion Capacitance Channelstop implant N A + W Bottom Side wall Source N x j Side wall L S Channel Substrate N A C diff = C bottom + C sw = C j AREA + C jsw PERIMETER = C j L S W + C jsw (L S + W) EE Junction Capacitance C j C j0 ( 1 V φ0 = m = 0.5: abrupt junction m m = 0.33: linear junction ) EE141 0
11 Linearizing the Junction Cap Replace nonlinear capacitance by largesignal equivalent linear capacitance which displaces equal charge over voltage swing of interest C eq = Q V j Q j ( v = V high high ) Q V j ( V low low ) = K eq C j0 K eq = ( V high φ V 1 m 1 m [( φ V ) ( φ V ] m 0 0 high 0 low low) (1 m) ) EE141 1 Capacitive evice Model G C gate = C GB + C GS + C G C GS C G = C GCS + C GSO = C GC + C GO S C SB C GB C B = C diff = C GCB = C diff B EE141
12 Capacitances in 0.5µm CMOS Process Textbook: page 11 EE141 3.MOEL Parameters MOS1.MOEL Modname NMOS/PMOS <VT0=VT0 > EE141 4
13 Two Inverters V PMOS In Out 1.µm =λ Metal1 Polysilicon NMOS GN EE141 5 Two Inverters (modern view) V EE141 6
14 Computing the Capacitances V V M C db C g4 M4 V in C gd1 M1 C db1 C w C g3 M3 Simplified Model V in C L Fanout EE141 7 The CMOS Inverter: C in S C gsp C in V in G C gdn,p C L C gsn S EE141 8
15 Miller Effect Z F i 1 = V in (1A) Z F i 1 V in A Z L i 1 = V in Z 1 V in i 1 A Z 1 Z Z L EE141 9 Miller Effect Z F A A Z 1 Z Z 1 = Z F 1 A Z = Z F 1 A 1 C 1 = C F (1 A) C 1 = C F (1 1/A) EE141 30
16 CMOS Inverter Example: C in C gsp C gs = C gsn + C gsp + V C gd  V C gd = C gdn + C gdp C in A = 1 C gsn C in = C gs + C gd (1A) EE The Miller Effect V C gd1 V V in V C gd1 C gd1 M1 V V in M1 A capacitor experiencing identical but opposite voltage swing at both terminals can be replaced by a capacitor to ground, whose value is two times the original value EE141 3
17 Computing the Capacitances V V M C db C g4 M4 V in C gd1 M1 C db1 C w C g3 M3 Simplified Model V in C L Fanout EE Computing the Capacitances EE141 34
18 Outline ynamic Operation of MOS Transistor MOS Capacitances Propagation elay EE CMOS Inverter Propagation elay: Approach 1 V t phl C = L V I swing avg I avg C L t phl CL ~ k V n V in = V EE141 36
19 CMOS Inverter Propagation elay: Approach V t phl = f ( R C ) L on = 0. 69R C on L ln(0.5) C L 1 V R n V in = V R on C L t EE MOS Transistor as a Switch V GS V T Traversed path S R on I V GS = V R mid R 0 V / V V S R R t t t 1 1 VS eq = avg( Ron( t)) = R ( ) = = on t dt t t1 t t1 t ) t1 t1 I t1 1 ( R ( t ) R ( )) eq on 1 + on t ( t) dt ( t EE141 38
20 The Transistor as a Switch V GS V T I V GS = V R on S R mid R 1 = ( R R ) eq mid + 0 R 0 V / V V S R R eq eq 1 = I 3 V 4 I SAT SAT V + ( 1+ λ V ) ( 1+ ) I SAT λ V 5 1 λ V 6 V EE Transient Response 3.5? t p = 0.69 C L (R eqn +R eqp )/ (V) t plh t phl t (sec) x EE141 40
21 esign for Performance Keep capacitances small Increase transistor sizes watch out for selfloading! Increase V (?) EE elay as a function of V t p (normalized) t phl 3 CL V = I SATn R eq = 0.5 ( W L) k ' V n n SATn CL V ( V V Tn V SATn ) V (V) EE141 4
22 evice Sizing 3.8 x (fixed load) t p (sec) Selfloading effect: Intrinsic capacitances dominate S EE NMOS/PMOS Ratio 5 x tplh tphl 4.5 t p (sec) 4 tp β = W p /W n β EE141 44
23 Impact of Rise Time on elay t phl (nsec) t rise (nsec) t p = t step(i) + η t step(i1) EE The SubMicron MOS Transistor Threshold Variations Subthreshold Conduction Parasitic Resistances EE141 46
24 Threshold Variations V T V T Longchannel threshold Low V S threshold L V S Threshold as a function of channel length (for low V S ) rain induced barrier lowering (IBL) (for low L) EE SubThreshold Conduction I (A) Quadratic Linear The Slope Factor I ~ I 0 e qvgs nkt, C n =1+ C S is V GS for I /I 1 =10 ox Exponential 101 V T V GS (V) Typical values for S: mv/decade EE141 48
25 SubThreshold I vs. V GS qvgs nkt I I0e 1 e qvs = kt I V S from 0 to 0.5V V GS EE SubThreshold I vs. V S I qvgs qvs = nkt kt I e 0 1 e ( 1+ λ V ) S I V GS from 0 to 0.3V V S EE141 50
26 Next Lecture Optimizing for Performance Power dissipation in CMOS inverters EE141 51
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