MOS Transistor Theory


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1 MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors as ideal switches An ON transistor passes a finite amount of current Depends on terminal voltages Derive currentvoltage (IV) relationships Transistor gate, source, drain all have capacitance I = C (ΔV/Δt) > Δt = (C/I) ΔV Capacitance and current determine speed Also explore what a degraded level really means EE 261 Krish Chakrabarty 2 1
2 MOS Transistor Theory Study conducting channel between source and drain Modulated by voltage applied to the gate (voltagecontrolled device) nmos transistor: majority carriers are electrons (greater mobility), psubstrate doped (positively doped) pmos transistor: majority carriers are holes (less mobility), nsubstrate (negatively doped) EE 261 Krish Chakrabarty 3 Terminal Voltages Mode of operation depends on V g, V d, V s + + V gs = V g V V gs s  V gd = V g V d V V ds = V d V s = V gs V s  gd V + ds Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage Hence V ds 0 nmos body is grounded. First assume source is 0 too. Three regions of operation Cutoff Linear Saturation V g V gd  V d EE 261 Krish Chakrabarty 4 2
3 Source Gate Biasing Gate SiO 2 Drain n + Channel n E psubstrate V gs =0: no current flows from source to drain (insulated by two reverse biased pn junctions V gs >0: electric field created across substrate V SS (Gnd) Electrons accumulate under gate: region changes from ptype to ntype Conduction path between source and drain EE 261 Krish Chakrabarty 5 psubstrate nmos Device Behavior Polysilicon gate Oxide insulator Inversion Region (ntype) Depletion region Depletion region V gs << V t Accumulation mode V gs = V t Depletion mode V gs > V t Inversion mode Enhancementmode transistor: Conducts when gate bias V gs > V t Depletionmode transistor: Conducts when gate bias is zero EE 261 Krish Chakrabarty 6 3
4 nmos Cutoff No channel I ds = 0 V gs = g +  V gd s n+ n+ ptype body b d EE 261 Krish Chakrabarty 7 nmos Linear Channel forms Current flows from d to s e  from s to d I ds increases with V ds Similar to linear resistor V gs > V t +  s g +  V gd = V gs n+ n+ V ds = 0 ptype body b d V gs > V t +  s g +  V gs > V gd > V t d I ds n+ n+ 0 < V ds < V gs V t ptype body b EE 261 Krish Chakrabarty 8 4
5 nmos Saturation Channel pinches off I ds independent of V ds We say current saturates Similar to current source V gs > V t +  g +  V gd < V t s d I ds n+ n+ V ds > V gs V t ptype body b EE 261 Krish Chakrabarty 9 IV Characteristics In linear region, I ds depends on How much charge is in the channel? How fast is the charge moving? EE 261 Krish Chakrabarty 10 5
6 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = gate t ox polysilicon gate n+ L n+ ptype body W SiO2 gate oxide (good insulator, ε ox = 3.9) V g + + source V gs C g V gd drain   channel n+  + n+ V s V ds ptype body V d EE 261 Krish Chakrabarty 11 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = CV C = t ox polysilicon gate n+ L n+ ptype body W SiO2 gate oxide (good insulator, ε ox = 3.9) V gs gate + V g + source C g V gd drain   channel n+  + n+ V s V ds ptype body V d EE 261 Krish Chakrabarty 12 6
7 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = CV C = C g = ε ox WL/t ox = C ox WL V = t ox polysilicon gate n+ L n+ ptype body W SiO2 gate oxide (good insulator, ε ox = 3.9) V gs gate + V g + source C g V gd drain   channel n+  + n+ V s C ox = ε ox / t ox V ds ptype body V d EE 261 Krish Chakrabarty 13 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = CV C = C g = ε ox WL/t ox = C ox WL C V = V gc V t = (V gs V ds /2) V ox = ε ox / t ox t gate t ox polysilicon gate n+ L n+ ptype body W SiO2 gate oxide (good insulator, ε ox = 3.9) V g + + source V gs C g V gd drain   channel n+  + n+ V s V ds ptype body V d EE 261 Krish Chakrabarty 14 7
8 Carrier velocity Charge is carried by e Carrier velocity v proportional to lateral Efield between source and drain v = EE 261 Krish Chakrabarty 15 Carrier velocity Charge is carried by e Carrier velocity v proportional to lateral Efield between source and drain v = μe μ called mobility E = EE 261 Krish Chakrabarty 16 8
9 Carrier velocity Charge is carried by e Carrier velocity v proportional to lateral Efield between source and drain v = μe μ called mobility E = V ds /L Time for carrier to cross channel: t = EE 261 Krish Chakrabarty 17 Carrier velocity Charge is carried by e Carrier velocity v proportional to lateral Efield between source and drain v = μe μ called mobility E = V ds /L Time for carrier to cross channel: t = L / v EE 261 Krish Chakrabarty 18 9
10 nmos Linear IV Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross I = ds EE 261 Krish Chakrabarty 19 nmos Linear IV Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross Qchannel Ids = t = EE 261 Krish Chakrabarty 20 10
11 nmos Linear IV Now we know I ds How much charge Q channel is in the channel How much time t each carrier takes to cross Qchannel = t W V = μc V V V L V = β V ds gs V t V 2 ds ds ox gs t 2 ds W β = μcox L EE 261 Krish Chakrabarty 21 nmos Saturation IV If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs V t Now drain voltage no longer increases current I ds = EE 261 Krish Chakrabarty 22 11
12 nmos Saturation IV If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs V t Now drain voltage no longer increases current V I dsat ds = β Vgs Vt V 2 dsat EE 261 Krish Chakrabarty 23 nmos Saturation IV If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs V t Now drain voltage no longer increases current V I dsat ds = β Vgs V t V 2 dsat β = ( V ) 2 gs Vt 2 EE 261 Krish Chakrabarty 24 12
13 nmos IV Summary Shockley 1 st order transistor models 0 Vgs < Vt V I = β V V ds V V V 2 < β ( V V ) 2 V > V 2 ds gs t ds ds dsat gs t ds dsat cutoff linear saturation EE 261 Krish Chakrabarty 25 CurrentVoltage Relations EE 261 Krish Chakrabarty 26 13
14 CurrentVoltage Relations k n : transconductance of transistor W : widthtolength ratio L As W increases, more carriers available to conduct current As L increases, V ds diminishes in effect (more voltage drop). Takes longer to push carriers across the transistor, reducing current flow EE 261 Krish Chakrabarty 27 For a 0.6 μm process From AMI Semiconductor t ox = 100 Å μ = 350 cm 2 /V*s V t = 0.7 V Plot I ds vs. V ds V gs = 0, 1, 2, 3, 4, 5 Use W/L = 4/2 λ Example A/ V L L L 14 W W W ox 8 β = μc = ( ) = μ I ds (ma) V gs = 2 V 0 gs = V ds V gs = 5 V gs = 4 V gs = 3 EE 261 Krish Chakrabarty 28 14
15 pmos IV All dopings and voltages are inverted for pmos Mobility μ p is determined by holes Typically 23x lower than that of electrons μ n 120 cm 2 /V*s in AMI 0.6 μm process Thus pmos must be wider to provide same current In this class, assume μ n / μ p = 2 to 3 EE 261 Krish Chakrabarty 29 Capacitance Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important Creates channel charge necessary for operation Source and drain have capacitance to body Across reversebiased diodes Called diffusion capacitance because it is associated with source/drain diffusion EE 261 Krish Chakrabarty 30 15
16 Gate Capacitance Approximate channel as connected to source C gs = ε ox WL/t ox = C ox WL = C permicron W C permicron is typically about 2 ff/μm polysilicon gate W t ox n+ L n+ ptype body SiO2 gate oxide (good insulator, ε ox = 3.9ε 0 ) EE 261 Krish Chakrabarty 31 The Gate Capacitance EE 261 Krish Chakrabarty 32 16
17 Diffusion Capacitance C sb, C db Undesirable, called parasitic capacitance Capacitance depends on area and perimeter Use small diffusion nodes Comparable to C g for contacted diff ½C g for uncontacted Varies with process EE 261 Krish Chakrabarty 33 Diffusion Capacitance EE 261 Krish Chakrabarty 34 17
18 G Parasitic Resistances Polysilicon gate L D Drain contact V GS,eff S R S R D D W Drain R S = (L S /W)R + R C R D = (L D /W)R + R C R C : contact resistance R : sheet resistance per square of drainsource diffusion EE 261 Krish Chakrabarty 35 Body Effect Many MOS devices on a common substrate Substrate voltage of all devices are normally equal But several devices may be connected in series Increase in sourcetosubstrate voltage as we proceed vertically along the chain V 12 g2 g1 V11 d2 s2 d1 s1 V sb2 = 0 V sb1 = 0 Net effect: slight increase in threshold voltage V t, V t2 >V t1 EE 261 Krish Chakrabarty 36 18
19 Pass Transistors We have assumed source is grounded What if source > 0? e.g. pass transistor passing EE 261 Krish Chakrabarty 37 Pass Transistors We have assumed source is grounded What if source > 0? e.g. pass transistor passing V g = If V s > V t, V gs < V t Hence transistor would turn itself off nmos pass transistors pull no higher than V tn Called a degraded 1 Approach degraded value slowly (low I ds ) pmos pass transistors pull no lower than V tp EE 261 Krish Chakrabarty 38 19
20 Pass Transistor Ckts V SS EE 261 Krish Chakrabarty 39 Pass Transistor Ckts Vs = V tn V DD Vtn VDDVtn V tn V s = V tp V tn 2V tn V SS EE 261 Krish Chakrabarty 40 20
21 Effective Resistance Shockley models have limited value Not accurate enough for modern transistors Too complicated for much hand analysis Simplification: treat transistor as resistor Replace I ds (V ds, V gs ) with effective resistance R I ds = V ds /R R averaged across switching of digital gate Too inaccurate to predict current at any given time But good enough to predict RC delay EE 261 Krish Chakrabarty 41 RC Delay Model Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nmos has resistance R, capacitance C Unit pmos has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width g d k s g d R/k kc s kc kc g d k s g s kc 2R/k kc kc d EE 261 Krish Chakrabarty 42 21
22 RC Values Capacitance C = C g = C s = C d = 2 ff/μm of gate width Values similar across many processes Resistance R 6 KΩ in 0.6um process Improves with shorter channel lengths Unit transistors May refer to minimum contacted device (4/2 λ) Or maybe 1 μm wide device Doesn t matter as long as you are consistent EE 261 Krish Chakrabarty 43 Activity 1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change EE 261 Krish Chakrabarty 44 22
23 Activity 1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change EE 261 Krish Chakrabarty 45 DC Response DC Response: vs. for a gate Ex: Inverter When = 0 > = When = > = 0 In between, depends on transistor size and current By KCL, must settle such that I dsn = I dsp We could solve equations But graphical solution gives more insight I dsp I dsn EE 261 Krish Chakrabarty 46 23
24 Transistor Operation Current depends on region of transistor behavior For what and are nmos and pmos in Cutoff? Linear? Saturation? EE 261 Krish Chakrabarty 47 Cutoff V gsn < nmos Operation Linear Saturated V gsn > V gsn > V dsn < V dsn > I dsp I dsn EE 261 Krish Chakrabarty 48 24
25 Cutoff nmos Operation Linear Saturated V gsn < V tn V gsn > V tn V gsn > V tn V dsn < V gsn V tn V dsn > V gsn V tn I dsp I dsn EE 261 Krish Chakrabarty 49 Cutoff nmos Operation Linear Saturated V gsn < V tn V gsn > V tn V gsn > V tn V dsn < V gsn V tn V dsn > V gsn V tn V gsn = I dsp V dsn = I dsn EE 261 Krish Chakrabarty 50 25
26 Cutoff nmos Operation Linear Saturated V gsn < V tn < V tn V gsn > V tn > V tn V dsn < V gsn V tn < V tn V gsn > V tn > V tn V dsn > V gsn V tn > V tn V gsn = I dsp V dsn = I dsn EE 261 Krish Chakrabarty 51 Cutoff V gsp > pmos Operation Linear Saturated V gsp < V gsp < V dsp > V dsp < I dsp I dsn EE 261 Krish Chakrabarty 52 26
27 Cutoff pmos Operation Linear Saturated V gsp > V tp V gsp < V tp V gsp < V tp V dsp > V gsp V tp V dsp < V gsp V tp I dsp I dsn EE 261 Krish Chakrabarty 53 Cutoff pmos Operation Linear Saturated V gsp > V tp V gsp < V tp V gsp < V tp V dsp > V gsp V tp V dsp < V gsp V tp V gsp =  V tp < 0 V dsp =  I dsp I dsn EE 261 Krish Chakrabarty 54 27
28 Cutoff pmos Operation Linear Saturated V gsp > V tp > + V tp V gsp < V tp < + V tp V dsp > V gsp V tp > V tp V gsp < V tp < + V tp V dsp < V gsp V tp < V tp V gsp =  V tp < 0 V dsp =  I dsp I dsn EE 261 Krish Chakrabarty 55 IV Characteristics Make pmos wider than nmos such that β n = β p V gsn5 I dsn V gsn4 V gsn3 V dsp V gsp1 V gsp20 V gsn2 V gsn1 V gsp3 V dsn V gsp4 I dsp V gsp5 EE 261 Krish Chakrabarty 56 28
29 A B DC Transfer Curve Transcribe points onto vs. plot C 0 D E V tn /2 +V tp EE 261 Krish Chakrabarty 57 Operating Regions Revisit transistor operating regions Region A B C D E nmos pmos A B 0 C D E V tn /2 +V tp EE 261 Krish Chakrabarty 58 29
30 Operating Regions Revisit transistor operating regions Region A B C D E nmos Cutoff Saturation Saturation Linear Linear pmos Linear Linear Saturation Saturation Cutoff A B 0 C D E V tn /2 +V tp EE 261 Krish Chakrabarty 59 Beta Ratio If β p / β n 1, switching point will move from /2 Called skewed gate Other gates: collapse into equivalent inverter β p 0.1 β = n β p 10 β = n EE 261 Krish Chakrabarty 60 30
31 Noise Margins How much noise can a gate input see before it does not recognize the input? Logical High Output Range Output Characteristics V OH NM H V IH V IL Input Characteristics Indeterminate Region Logical High Input Range Logical Low Output Range V OL NM L GND Logical Low Input Range EE 261 Krish Chakrabarty 61 Logic Levels To maximize noise margins, select logic levels at β p /β n > 1 0 EE 261 Krish Chakrabarty 62 31
32 Logic Levels To maximize noise margins, select logic levels at unity gain point of DC transfer characteristic Unity Gain Points Slope = 1 V OH β p /β n > 1 V OL 0 V tn V IL V IH  V tp EE 261 Krish Chakrabarty 63 32
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