The CMOS Inverter: A First Glance


 Charlene Bridges
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1 The CMOS Inverter: A First Glance V DD S D V in V out C L D S
2 CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND
3 CMOS Inverter: Steady State Response V DD V DD V OL = 0 V OH = V DD V M = f(r n, R p ) R p V out = 1 V out = 0 R n V in = 0 V in = V DD
4 CMOS Inverter: Transient Response V DD V DD R p t phl = f(r on.c L ) = 0.69 R on C L V out V out C L C L R n V in 5 0 = = V in 5 V DD (a) Lowtohigh (b) Hightolow
5 CMOS Properties Full railtorail swing high noise margins Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady state low output impedance (output resistance in kω range) large fanout (less sensitive to noise as well) Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steadystate input current No direct path steadystate between power and ground no static power dissipation Propagation delay function of load capacitance and resistance of transistors (limits fanout)
6 Review: Short Channel IV Plot (NMOS) 2.5 X 104 V GS = 2.5V 2 I D (A) V GS = 2.0V V GS = 1.5V V GS = 1.0V Linear dependence V DS (V) NMOS transistor, 0.25um, L d = 0.25um, W/L = 1.5, V DD = 2.5V, V T = 0.4V
7 Review: Short Channel IV Plot (PMOS) All polarities of all voltages and currents are reversed 2 V DS (V) V GS = 1.0V 0.2 V GS = 1.5V V GS = 2.0V I D (A) 0.8 V GS = 2.5V 1 X 104 PMOS transistor, 0.25um, L d = 0.25um, W/L = 1.5, V DD = 2.5V, V T = 0.4V
8 Transforming PMOS IV Lines Want common coordinate set V in, V out, and I dn (loadline plot) I DSp = I DSn V GSn = V in ; V GSp = V in V DD V DSn = V out ; V DSp = V out V DD I Dn In V DD PMOS Out NMOS V out I D p V in = 0 I Dn V in = 0 I Dn V in = 1.5 V in = 1.5 V DS p V DS p V GSp = 1 V GSp = 2.5 Mirror around xaxis V in = V DD + V GSp I Dn = I Dp Horiz. shift over V DD V out = V DD + V DSp V out
9 CMOS Inverter Load Lines PMOS 2,5 X 104 NMOS V in = 0V V in = 2.5V 2 I Dn (A) V in = 0.5V V in = 1.0V 1,5 1 V in = 2V 0,5 V in = 1.5V V in = 2.0V 0 V in = 2.5V V in = 1.5V V in = 1V 0 0,5 1 1,5 2 2,5 V out (V) V in = 2.0V V in = 1.5V V in = 0.5V V in = 1.0V V in = 0.5V V in = 0V 0.25um, W/L n = 1.5, W/L p = 4.5, V DD = 2.5V, V Tn = 0.4V, V Tp = 0.4V
10 CMOS Inverter VTC NMOS off PMOS res NMOS sat PMOS res V out (V) V in (V) NMOS sat PMOS sat NMOS res PMOS sat V DS =V GS NMOS res PMOS off
11 The response of the inverter is dominated mainly by the output capacitance of the gate C L, which is composed of:  Drain diffusion capacitance of PMOS & NMOS transistors  Capacitances of connecting wires  Input capacitance of the fanout gates A fast gate is built either by keeping the output capacitance small or by decreasing the onresistance of the transistor. The latter is achieved by increasing the W/L ratio.
12 Relative Transistor Sizing When designing static CMOS circuits, balance the driving strengths of the transistors by making the PMOS section wider than the NMOS section to maximize the noise margins and obtain symmetrical characteristics
13 Switching Threshold as a function of Transistor Ratio In the transition region both PMOS and NMOS transistors are always saturated, since V DS = V GS. By equating the currents through the transistors (assuming velocity saturation and ignoring channel length modulation): V in = V out = V M, V GS = V M (NMOS), V GS = V M V DD (PMOS)
14 Switching Threshold V M where V in = V out (both PMOS and NMOS in saturation since V DS = V GS ). For large values of V DD (wrt treshold & saturation voltages): V M rv DD /(1 + r) where r = k p V DSATp /k n V DSATn Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors For V M to be at V DD /2, r 1 which is equivalent to sizing the PMOS device so that: (W/L) p = (W/L) n x (V DSATn k n )/(V DSATp k p ) To move V M upwards, a larger value of r is required, which means making PMOS wider.
15 The required ratio of PMOS to NMOS transistor sizes such that switching treshold is set to a desired value V M ( W / L) p k' n VDSATn( VM VTn VDSATn /2) = ( W / L) k' V ( V V + V + V /2) n p DSATp DD M Tp DSATp For long channel devices or when supply voltage is low (no velocity saturation): V M V + r( V + V ) k =, r = 1+ r k Tn DD Tp p n
16 Switching Threshold Example In our generic 0.25 micron CMOS process, using the process parameters V DD = 2.5V, and a minimum size NMOS device ((W/L) n of 1.5) NMOS PMOS V T0 (V) γ(v 0.5 ) V DSAT (V) k (A/V 2 ) 115 x x 106 λ(v 1 ) For V M = 1.25V (half of V DD ): (W/L) p 115 x ( /2) = x x = 3.5 (W/L) n 30 x ( /2) (W/L) p = 3.5 x 1.5 = 5.25 for a V M of 1.25V
17 Simulated Inverter V M V M (V) ~ (W/L) p /(W/L) n Note: xaxis is semilog V M is relatively insensitive to variations in device ratio setting the ratio to 3, 2.5 and 2 gives V M s of 1.22V, 1.18V, and 1.13V Increasing the width of the PMOS moves V M towards V DD Increasing the width of the NMOS moves V M toward GND
18 a) Response of standard inverter b)response of modified treshold
19 Noise Margins Determining V IH and V IL 3 V OH = V DD 2 V DD V M By definition, V IH and V IL are where dv out /dv in = 1 (= gain) V IH V IL =(V OH V OL )/g=v DD /g V out 1 V OL = GND 0 VIL V M V in A piecewise linear approximation of VTC VIH NM H = V DD V IH NM L = V IL GND Approximating: V IH = V M V M /g V IL = V M + (V DD V M )/g So high gain in the transition region is very desirable
20 Gain Determinates gain V in dv out /dv in = Gain is a strong function of the slopes of the currents in the saturation region, for V in = V M (1+r) g (V M V Tn V DSATn /2)(λ  λ n p ) Determined by technology parameters, especially channel length modulation (λ). Only designer influence through supply voltage and V M (transistor sizing).
21 Impact of Process Variation on VTC Curve V out (V) 2,5 2 1,5 1 0,5 0 Bad PMOS Good NMOS Good PMOS Bad NMOS Nominal 0 0,5 1 1,5 2 2,5 V in (V) rocess variations (mostly) cause a shift in the switching threshold
22 Gain as a function of VDD ) (V t V ou ) (V t V ou V (V) in 0.05 Gain= V (V) in
23 Why don t we operate at low supply voltages? Reducing the supply voltage improves gain and energy dissipation. But severely degrades the delay of the gate The dc characteristic becomes increasingly sensitive to variations in the device parameters While it helps to reduce the internal noise (such as crosstalk), it makes the device more sensitive to external noise sources that do not scale. To achieve sufficient gain for use in a digital circuit, it is necessary that the supply be at least 4φ T where φ T = kt/q (the only way to operate CMOS inverters below 100mV is to reduce the ambient temperature, that is to cool the circuit)
24
25 Diffusion capacitances C db1 and C db2 C = K C eq eq j0 Φ K V V m 0 1 m 1 m eq = ( Φ0 high) ( Φ0 low) ( Vhigh Vlow)(1 m)
26
27 Gate Capacitances of FanOut C g3 and C g4 C fanout = C gate (NMOS) + C gate (PMOS) = (C GSOn + C GDOn + W n L n C ox ) + (C GSOp + C GDOp + W p L p C ox ) From Table 35:
28 CMOS Inverters 5λx9λ V DD PMOS (9λ/2λ) 0.25µm = 2λ 4λx4λ In Out Metal1 3λx1λ Polysilicon NMOS (3λ/2λ) GND =15λ (perimeter of drain area)
29
30 PRORAGATION DELAY V2 dv C CL I = C dt = dv t p dv dt I = i V 1 both C and i are nonlinear functions of V an exact computation of this L equation is very difficult. Instead, we use the simplified switch model. R v out v out (t) = (1 e t/τ )V where τ = RC v in C Time to reach 50% point is t = ln(2) τ = 0.69 τ
31 Inverter Propagation Delay Propagation delay is proportional to the timeconstant of the network formed by the pulldown resistor and the load capacitance V DD t phl = f(r n, C L ) R n C L V out = 0 t phl = ln(2) R eqn C L = 0.69 R eqn C L t plh = ln(2) R eqp C L = 0.69 R eqp C L V in = V DD t p = (t phl + t plh )/2 = 0.69 C L (R eqn + R eqp )/2 To equalize rise and fall times make the onresistance of the NMOS and PMOS approximately equal.
32 Transient Response 3 2.5? t p = (t phl +t plh )/ ps t p = 0.69 C L (R eqn +R eqp )/ t phl 39.9ps t plh x 1010
33 Inverter Transient Response V out (V) 3 2,5 2 1,5 1 0,5 00,5 V in 0 0,5 1 1,5 2 2,5 t (sec) x V DD =2.5V 0.25µm W/L n = 1.5 W/L p = 4.5 R eqn = 13 kω ( 1.5) R eqp = 31 kω ( 4.5) t f t t phl = / t r phl t plh t plh = /4.5 6 t phl = 36 psec t plh = 29 psec so t p = 32.5 psec From simulation: t phl = 39.9 psec and t plh = 31.7 psec
34 Delay as a function of V DD Ignoring channel length modulation 4.5 t p (normalized) if V >> V + V / 2 t phl DD Tn DSATn CL 0.52 ( W / L ) k ' V n n DSATn 1.5 Independent of V DD V DD (V) Dots indicate the values calculated. Assumed velocity sat. Deviation at low supply voltages
35 Design for Performance Keep capacitances small Good design practice requires keeping the drain diffusion areas as small as possible Increase transistor sizes watch out for selfloading! intrinsic capacitance (i.e. diffusion capacitance) starts to dominate extrinsic load (wiring & f.out) Increase V DD (????) trade off energy dissipation oxide breakdown, hot carrier effects minimal improvement above a certain level
36 So far we have considered widened PMOS so that its resistance matches that of the pulldown NMOS to yield symmetrical VTC. However, this does not imply that this ratio also yields the minimum overall propagation delay. If symmetry and reduced noise margins are not of prime concern, it is possible to speed up the inverter by reducing the width of the PMOS device. Consider the 2 identical cascaded CMOS inverters, with approximate load capacitance of the 1. Gate C L :
37 NMOS to PMOS Ratio C = ( C + C ) + ( C + C ) + C L dp1 dn1 gp2 gn2 w β = ( W/ L) /( W/ L) C = βc, C = βc p n dp1 dn1 gp2 gn2 C β C C C t C eqn eqp L = (1 + )( dn1+ gn2) + w since p = 0.69 L 0.69 Reqp tp = (1 β )( Cdn 1 Cgn2 ) C w R eqn β dn1 gn2 w eqn eqp eqn R + R r = (1 + β)( C + C ) + C R 1 + where, r = R /R β to find the optimal value of β, setting t / β = 0 we find β = r 1 + C or β = r when C + C >> C w opt opt dn1 gn2 w Cdn 1+ C gn2 p 2
38 NMOS/PMOS ratio 5 x t p (s e c) tplh tphl tp β of 2.4 (= 31 kω/13 kω) gives symmetrical response β= 31kΩ/13k Ω =2.4 β of 1.9 gives optimal performance (1.6 calculated) β
39 NMOS/PMOS Ratio So far have sized the PMOS and NMOS so that the R eq s match (ratio of 3 to 3.5) symmetrical VTC equal hightolow and lowtohigh propagation delays If speed is the only concern, reduce the width of the PMOS device! widening the PMOS degrades the t phl due to larger parasitic capacitance β = (W/L p )/(W/L n ) r = R eqp /R eqn (resistance ratio of identicallysized PMOS and NMOS) β opt = r when wiring capacitance is negligible
40 The next question is how transistor sizing (sizing both NMOS and PMOS with the same ratio) impacts the performance of the gate. To answer this question, we must use a sizing factor S, which relates the transistor sizes of our inverter to a reference gate, typically a minimum sized inverter.
41 Device Sizing for Performance Divide capacitive load, C L, into C int : intrinsic  diffusion and Miller effect C ext : extrinsic  wiring and fanout t = 0.69R ( C + C ) p eq int ext t p = 0.69 R eq C int (1 + C ext /C int ) = t p0 (1 + C ext /C int ) where t p0 = 0.69 R eq C int is the intrinsic (unloaded) delay of the gate (C ext = 0) Widening both PMOS and NMOS by a factor S reduces R eq by an identical factor (R eq = R ref /S), but raises the intrinsic capacitance by the same factor (C int = SC iref ) t p = 0.69 R ref C iref (1 + C ext /(SC iref )) = t p0 (1 + C ext /(SC iref )) t p0 is independent of the sizing of the gate; with no load the drive of the gate is totally offset by the increased capacitance any S sufficiently larger than (C ext /C int ) yields the best performance gains with least silicon area impact
42 Sizing Impacts on Delay t p (sec) x for a fixed load The majority of the improvement is already obtained for S = 5. Sizing factors larger than 10 barely yield any extra gain (and cost significantly more area) S selfloading effect (intrinsic capacitance dominates)
43 Sizing a Chain of Inverters While sizing up an inverter reduces its delay, it also increases its input capacitance. Gate sizing without taking into account its impact on the delay of the preceding gates is a purely academic enterprise. Therefore, a more relevant problem is determining the optimum sizing of a gate when embedded in a real environment.
44 Impact of Fanout on Delay Extrinsic capacitance, C ext, is a function of the fanout of the gate  the larger the fanout, the larger the external load. First determine the input loading effect of the inverter. Both input gate capacitance C g and intrinsic output capacitance C int are proportional to the gate sizing, so C int = γc g is independent of gate sizing and t p = t p0 (1 + C ext / γc g ) = t p0 (1 + f/γ) i.e., the delay of an inverter is a function of the ratio between its external load capacitance and its input gate capacitance: the effective fanout f f = C ext /C g
45 Inverter Chain Real goal is to minimize the delay through an inverter chain In C g,1 1 2 N C L Out the delay of the jth inverter stage is (C W ignored): t p,j = t p0 (1 + C g,j+1 /(γc g,j )) = t p0 (1 + f j / γ) and t p = t p1 + t p t pn so t p = t p,j = t p0 (1 + C g,j+1 /(γc g,j )), with C g,n+1 =C L If C L is given How should the inverters be sized? How many stages are needed to minimize the delay?
46 This equation has N1unknowns, being C g,2, C g,3,... C g,n. The minimum delay can be found by taking N1 partial derivatives and equating them to zero: t C p g, j The result is a set of constraints: C C = C g, j+ 1 g, j C g, j g, j 1 = 0 with (j=2,... N) In other words, the optimum size of each inverter is the geometric mean of its neighbors sizes: C = C C g, j g, j 1 g, j + 1
47 Sizing the Inverters in the Chain The optimum size of each inverter is the geometric mean of its neighbors meaning that if each inverter is sized up by the same factor f wrt the preceding gate, it will have the same effective fanout and the same delay N f = C L /C g,1 = F where F represents the overall effective fanout of the circuit (F = C L /C g,1 = f N ) and the minimum delay through the inverter chain is t p = N t p0 (1 + ( F ) / γ) The relationship between t p and F is linear for one inverter, square root for two, etc. N N
48 Example of Inverter Chain Sizing In Out C g,1 1 f = 2 f 2 = 4 C L = 8 C g,1 C L /C g,1 has to be evenly distributed over N = 3 inverters C L /C g,1 = 8/1 3 f = 8 = 2
49 Determining N: Optimal Number of Inverters What is the optimal value for N given F (=f N )? if the number of stages is too large, the intrinsic delay of the stages becomes dominant if the number of stages is too small, the effective fanout of each stage becomes dominant (1 N t / ) p = Ntp0 + F γ The optimum N is found by differentiating the minimum delay expression and setting the result to 0, giving N (1 / f ) N F ln F γ + F = 0 or equivalently: f = e + γ N For γ = 0 (selfloading is ignored) N = ln (F) and the effectivefan out becomes f = e = For γ = 1 (the typical case) the optimum effective fanout (tapering factor) turns out to be close to 3.6
50 Optimum Effective FanOut 5 7 F opt normalized delay γ = γ Choosing f larger than optimum has little effect on delay and reduces the number of stages (and area). Common practice to use f = 4 (for γ = 1) But too many stages has a substantial negative impact on delay f
51 Example of Inverter (Buffer) Staging N f t p 1 C g,1 = 1 C L = 64 C g, C g,1 = 1 C L = 64 C g, C g,1 = 1 C L = 64 C g, C g,1 = 1 C L = 64 C g,1
52 Impact of Buffer Staging for Large C L F (γ = 1) 10 Unbuffered 11 Two Stage Chain 8.3 Opt. Inverter Chain 8.3 N ,000 10, , Impressive speedups with optimized cascaded inverter chain for very large capacitive loads.
53 Input Signal Rise/Fall Time In reality, the input signal changes gradually (and both PMOS and NMOS conduct for a brief time). This affects the current available for charging/discharging C L and impacts propagation delay. t p increases linearly with increasing input slope, t s, once t s > t p t p (sec) t s is due to the limited driving capability of the preceding gate 5,4 5,2 5 4,8 4,6 4,4 4,2 4 3,8 3,6 x t s (sec) for a minimumsize inverter with a fanout of a single gate x 1011
54 Design Challenge A gate is never designed in isolation: its performance is affected by both the fanout and the driving strength of the gate(s) feeding its inputs. t i p = ti step + η ti1 step (η 0.25) Keep signal rise times smaller than or equal to the gate propagation delays. good for performance good for power consumption Keeping rise and fall times of the signals small and of approximately equal values is one of the major challenges in highperformance designs  slope engineering.
55 Delay with Long Interconnects When gates are farther apart, wire capacitance and resistance can no longer be ignored. V in (r w, c w, L) V out c int c fan t p = 0.69R dr C int + (0.69R dr +0.38R w )C w (R dr +R w )C fan where R dr = (R eqn + R eqp )/2 = 0.69R dr (C int +C fan ) (R dr c w +r w C fan )L r w c w L 2 Wire delay rapidly becomes the dominate factor (due to the quadratic term) in the delay budget for longer wires.
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