CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)


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1 CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L04 S.1
2 Review: The MOS Transistor Source n+ W Polysilicon Gate L Gate oxide Drain n+ FieldOxide (SiO 2 ) p substrate Bulk (Body) CMPEN 411 L04 S.2
3 CMOS Inverter: A First Look V DD V in V out C L CMPEN 411 L04 S.3
4 CMOS Inverter: Steady State Response V DD V DD V OL = 0 V OH = V DD V M = f(r n, R p ) R p V out = 1 V out = 0 R n V in = 0 V in = V DD CMPEN 411 L04 S.4
5 CMOS Properties Full railtorail swing high noise margins Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady state low output impedance (output resistance in k range) large fanout (albeit with degraded performance) Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steadystate input current No direct path steadystate between power and ground no static power dissipation Propagation delay is a function of load capacitance and resistance of transistors CMPEN 411 L04 S.5
6 Review: Short Channel IV Plot (NMOS) X 104 V GS = 2.5V V GS = 2.0V V GS = 1.5V 0.5 V GS = 1.0V V DS (V) NMOS transistor, 0.25um, L d = 0.25um, W/L = 1.5, V DD = 2.5V, V T = 0.4V CMPEN 411 L04 S.6
7 Review: Short Channel IV Plot (PMOS) All polarities of all voltages and currents are reversed 2 V DS (V) V GS = 1.0V 0.2 V GS = 1.5V 0.4 V GS = 2.0V V GS = 2.5V 1 X 104 PMOS transistor, 0.25um, L d = 0.25um, W/L = 1.5, V DD = 2.5V, V T = 0.4V CMPEN 411 L04 S.7
8 Transforming PMOS IV Lines Want common coordinate set V in, V out, and I Dn I DSp = I DSn V GSn = V in ; V GSp = V in  V DD V DSn = V out ; V DSp = V out  V DD I Dn Vout V in = 0 V in = 1.5 V in = 0 V in = 1.5 V GSp = 1 V GSp = 2.5 Mirror around xaxis V in = V DD + V GSp I Dn = I Dp Horiz. shift over V DD V out = V DD + V DSp CMPEN 411 L04 S.8
9 CMOS Inverter Load Lines PMOS V in = 0V X 104 NMOS V in = 2.5V V in = 0.5V 1.5 V in = 2.0V V in = 1.0V 1 V in = 2V 0.5 V in = 1.5V V in = 2.0V V in = 2.5V 0 V in = 1.5V V in = 1V V out (V) V in = 1.5V V in = 0.5V V in = 1.0V V in = 0.5V V in = 0V 0.25um, W/L n = 1.5, W/L p = 4.5, V DD = 2.5V, V Tn = 0.4V, V Tp = 0.4V CMPEN 411 L04 S.9
10 V out (V) CMOS Inverter VTC NMOS off PMOS linear NMOS sat PMOS linear V in (V) NMOS sat PMOS sat NMOS linear PMOS sat NMOS linear PMOS off CMPEN 411 L04 S.10
11 CMOS Inverter: Switch Model of Dynamic Behavior V DD V DD R p V out V out C L R n C L V in = 0 V in = V DD Gate response time is determined by the time to charge C L through R p (discharge C L through R n ) CMPEN 411 L04 S.11
12 Relative Transistor Sizing When designing static CMOS circuits, balance the driving strengths of the transistors by making the PMOS section wider than the NMOS section to maximize the noise margins and obtain symmetrical characteristics CMPEN 411 L04 S.12
13 Switching Threshold V M where V in = V out (both PMOS and NMOS in saturation since V DS = V GS ) V M rv DD /(1 + r) where r = k p V DSATp /k n V DSATn Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors Want V M = V DD /2 (to have comparable high and low noise margins), so want r 1 (W/L) p k n V DSATn (V M V Tn V DSATn /2) = (W/L) n k p V DSATp (V DD V M +V Tp +V DSATp /2) CMPEN 411 L04 S.13
14 Switch Threshold Example In our generic 0.25 micron CMOS process, using the process parameters from slide L03.26, a V DD = 2.5V, and a 1.5 size NMOS device (W/L) n V T0 (V) (V 0.5 ) V DSAT (V) k (A/V 2 ) (V 1 ) NMOS x PMOS x (W/L) p 115 x ( /2) = x x = 3.5 (W/L) n 30 x ( /2) (W/L) p = 3.5 x 1.5 = 5.25 for a V M of 1.25V CMPEN 411 L04 S.15
15 Simulated Inverter V M ~ (W/L) p /(W/L) n Note: xaxis is semilog V M is relatively insensitive to variations in device ratio setting the ratio to 3, 2.5 and 2 gives V M s of 1.22V, 1.18V, and 1.13V Increasing the width of the PMOS moves V M towards V DD Increasing the width of the NMOS moves V M toward GND CMPEN 411 L04 S.16
16 Noise Margins Determining V IH and V IL 3 By definition, V IH and V IL are where dv out /dv in = 1 (= gain) V OH = V DD 2 1 V M NM H = V DD  V IH NM L = V IL  GND Approximating: V IH = V M  V M /g V IL = V M + (V DD  V M )/g V OL = GND0 VIL V in A piecewise linear approximation of VTC VIH So high gain in the transition region is very desirable CMPEN 411 L04 S.17
17 Gain Determinates V in Gain is a strong function of the slopes of the currents in the saturation region, for V in = V M (1+r) g (V M V Tn V DSATn /2)( n  p ) Determined by technology parameters, especially channel length modulation ( ). Only designer influence through supply voltage and V M (transistor sizing). CMPEN 411 L04 S.18
18 V out (V) CMOS Inverter VTC from Simulation V in (V) 0.25um, (W/L) p /(W/L) n = 3.4 (W/L) n = 1.5 (min size) V DD = 2.5V V M 1.25V, g = V IL = 1.2V, V IH = 1.3V NM L = NM H = 1.2 (actual values are V IL = 1.03V, V IH = 1.45V NM L = 1.03V & NM H = 1.05V) Output resistance lowoutput = 2.4k highoutput = 3.3k CMPEN 411 L04 S.19
19 V out (V) V out (V) Scaling the Supply Voltage V in (V) Gain= V in (V) Device threshold voltages are kept (virtually) constant Device threshold voltages are kept (virtually) constant CMPEN 411 L04 S.21
20 Next Lecture and Reminders Next lecture IC manufacturing  Reading assignment Rabaey, et al, CMPEN 411 L04 S.22
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