Lecture 4: CMOS Transistor Theory


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1 Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh
2 Outline q Introduction q MOS Capacitor q nmos IV Characteristics q pmos IV Characteristics q Gate and Diffusion Capacitance q Pass Transistors q RC Delay Models 3: CMOS Transistor Theory CMOS VLSI Design Slide 2
3 Introduction q So far, we have treated transistors as ideal switches q An ON transistor passes a finite amount of current Depends on terminal voltages Derive currentvoltage (IV) relationships q Transistor gate, source, drain all have capacitance I = C (ΔV/Δt) > Δt = (C/I) ΔV Capacitance and current determine speed q Also explore what a degraded level really means 3: CMOS Transistor Theory CMOS VLSI Design Slide 3
4 MOS Transistors  Types and Symbols D D G G S NMOS Enhancement NMOS D S Depletion D G G B PMOS S Enhancement S NMOS with Bulk Contact Digital Integrated Circuits 2nd Devices
5 The MOS Transistor Polysilicon Aluminum Digital Integrated Circuits 2nd Devices
6 Controlling current flow in an nfet. Digital Integrated Circuits 2nd Introduction to Circuits, Fourth Edition by Peter Uyemura, Devices Copyright 2004 John Wiley & Sons. All rights reserved.
7 Controlling current flow in a pfet. Digital Integrated Circuits 2nd Introduction to Circuits, Fourth Edition by Peter Uyemura, Devices Copyright 2004 John Wiley & Sons. All rights reserved.
8 What is a Transistor? A Switch! A MOS Transistor V GS V T R o n V GS S D Digital Integrated Circuits 2nd Devices
9 IV Curves Current (I) vs. Voltage (V) I = f(v) 6 x I D (A) Resistor I = V/R Diode I = Is*exp(k*VVt) V DS MOS I = f(vgs, Vds)
10 Terminal Voltages q Mode of operation depends on V g, V d, V s V gs = V g V s V gd = V g V d V gs  + V g + V gd  q q q V ds = V d V s = V gs  V V gd s Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage Hence V ds 0 nmos body is grounded. First assume source is 0 too. Three regions of operation Cutoff Linear Saturation  V + ds V d 3: CMOS Transistor Theory CMOS VLSI Design Slide 10
11 MOS Capacitor q Gate and body form MOS capacitor q Operating modes Accumulation Depletion Inversion In general, MOS gate capacitance is not constant (a) (b) V g < polysilicon gate silicon dioxide insulator ptype body 0 < V g < V t depletion region V g > V t +  inversion region depletion region (c) 3: CMOS Transistor Theory CMOS VLSI Design Slide 11
12 MOS Transistors Operating regions Digital Integrated Circuits 2nd Devices Copyright 2005 Pearson AddisonWesley. All rights reserved.
13 nmos Cutoff q No channel q I ds = 0 d V gs = g +  V gd g s n+ n+ d s ptype body b 3: CMOS Transistor Theory CMOS VLSI Design Slide 13
14 nmos Linear q Channel forms q Current flows from d to s e  from s to d q I ds increases with V ds q Similar to linear resistor g s d V gs > V t V gs > V t V gd = V gs n+ n+ V ds = 0 ptype body b +  s s g g +  V gs > V gd > V t n+ n+ 0 < V ds < V gs V t ptype body b d d I ds 3: CMOS Transistor Theory CMOS VLSI Design Slide 14
15 Linear Region V gs >V t & V gd >V t S V GS G V DS D I D I ds n + V(x) + n + V gd L psubstrate x V gs R Positive Charge on Gate: Channel exists, Current Flows since V ds > 0 I ds = k (W/L)((V gs V t )V ds V ds2 /2) B I ds I=V/R R= 1/(k (W/L)(V gs V t )) V ds Digital Integrated Circuits 2nd Devices
16 nmos Saturation q Channel pinches off q I ds independent of V ds q We say current saturates q Similar to current source g d V gs > V t +  s g +  V gd < V t d I ds s n+ n+ ptype body b V ds > V gs V t 3: CMOS Transistor Theory CMOS VLSI Design Slide 16
17 Saturation: V gs >V t & V gd <V t V GS I ds S G V DS > V GS  V T D V gd I ds n+  V GS  V T + n+ V gs Positive Charge on Gate: Channel exists, Current Flows since V ds > 0 But: channel is pinched off I ds = (k /2)(W/L)(V gs V t ) 2 Digital Integrated Circuits 2nd Devices
18 IV Characteristics q In Linear region, I ds depends on How much charge is in the channel? How fast is the charge moving? 3: CMOS Transistor Theory CMOS VLSI Design Slide 18
19 MOS Transistors Regions Transitions Digital Integrated Circuits 2nd Devices Copyright 2005 Pearson AddisonWesley. All rights reserved.
20 Channel Charge q MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel q Q channel = gate t ox L n+ n+ ptype body polysilicon gate W SiO2 gate oxide (good insulator, ε ox = 3.9) V g + + source V gs C g V gd drain   channel n+  + n+ V s V ds ptype body V d 3: CMOS Transistor Theory CMOS VLSI Design Slide 20
21 Channel Charge q MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel q Q channel = CV q C = gate t ox L n+ n+ ptype body polysilicon gate W SiO2 gate oxide (good insulator, ε ox = 3.9) V g + + source V gs C g V gd drain   channel n+  + n+ V s V ds ptype body V d 3: CMOS Transistor Theory CMOS VLSI Design Slide 21
22 Channel Charge q MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel q Q channel = CV q C = C g = ε ox WL/t ox = C ox WL q V = C ox = ε ox / t ox C ox = 8.6*fF/um 2 gate t ox L n+ n+ ptype body polysilicon gate W SiO2 gate oxide (good insulator, ε ox = 3.9) V g + + source V gs C g V gd drain   channel n+  + n+ V s V ds ptype body V d 3: CMOS Transistor Theory CMOS VLSI Design Slide 22
23 Channel Charge q MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel q Q channel = CV q C = C g = ε ox WL/t ox = C ox WL q V = V gc V t = (V gs V ds /2) V t C ox = ε ox / t ox gate t ox L n+ n+ ptype body polysilicon gate W SiO2 gate oxide (good insulator, ε ox = 3.9) V g + + source V gs C g V gd drain   channel n+  + n+ V s V ds ptype body V d 3: CMOS Transistor Theory CMOS VLSI Design Slide 23
24 Carrier velocity q Charge is carried by e q Carrier velocity v proportional to lateral Efield between source and drain q v = 3: CMOS Transistor Theory CMOS VLSI Design Slide 24
25 Carrier velocity q Charge is carried by e q Carrier velocity v proportional to lateral Efield between source and drain q v = µe µ called mobility q E = 3: CMOS Transistor Theory CMOS VLSI Design Slide 25
26 Carrier velocity q Charge is carried by e q Carrier velocity v proportional to lateral Efield between source and drain q v = µe µ called mobility q E = V ds /L q Time for carrier to cross channel: t = 3: CMOS Transistor Theory CMOS VLSI Design Slide 26
27 Carrier velocity q Charge is carried by e q Carrier velocity v proportional to lateral Efield between source and drain q v = µe µ called mobility q E = V ds /L q Time for carrier to cross channel: t = L / v 3: CMOS Transistor Theory CMOS VLSI Design Slide 27
28 nmos Linear IV q Now we know How much charge Q channel is in the channel I ds = How much time t each carrier takes to cross 3: CMOS Transistor Theory CMOS VLSI Design Slide 28
29 nmos Linear IV q Now we know How much charge Q channel is in the channel I ds How much time t each carrier takes to cross = = Q channel t 3: CMOS Transistor Theory CMOS VLSI Design Slide 29
30 nmos Linear IV q Now we know How much charge Q channel is in the channel I ds How much time t each carrier takes to cross Qchannel = t W V = µ C V V V L V = β V ds gs V t V 2 ds ds ox gs t 2 ds W β = µcox L 3: CMOS Transistor Theory CMOS VLSI Design Slide 30
31 Computed Curves Linear Resistor Vgs = 5v Vgs = 4.5v Vgs = 4.0v Digital Integrated Circuits 2nd Devices
32 nmos Saturation IV q If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs V t q Now drain voltage no longer increases current I ds = 3: CMOS Transistor Theory CMOS VLSI Design Slide 32
33 nmos Saturation IV q If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs V t q Now drain voltage no longer increases current V I = β V V dsat V 2 ds gs t dsat 3: CMOS Transistor Theory CMOS VLSI Design Slide 33
34 nmos Saturation IV q If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs V t q Now drain voltage no longer increases current V I = β V V dsat V 2 β = ( V ) 2 gs Vt 2 ds gs t dsat 3: CMOS Transistor Theory CMOS VLSI Design Slide 34
35 Computed Curves Linear Resistor Vgs = 5v Vgs = 4.5v Vgs = 4.0v 3: CMOS Transistor Theory CMOS VLSI Design Slide 35
36 nmos IV Summary q Shockley 1 st order transistor models 0 Vgs < V V I = β V V ds V V V 2 < β ( V V ) 2 V > V 2 ds gs t ds ds dsat gs t ds dsat t cutoff linear saturation 3: CMOS Transistor Theory CMOS VLSI Design Slide 36
37 Example q We will be using a µm process for your project From TSMC Semiconductor t ox = 40 Å µ = 180 cm 2 /V*s V t = 0.4 V q Plot I ds vs. V ds V gs = 0, 0.3,, 1.8 Use W/L = 4/2 λ 14 W W W β = µ Cox = ( ) 120 µ A/ V 8 L = L L 2 3: CMOS Transistor Theory CMOS VLSI Design Slide 37
38 pmos IV q All dopings and voltages are inverted for pmos q Mobility µ p is determined by holes Typically 23x lower than that of electrons µ n q Thus pmos must be wider to provide same current Often, assume µ n / µ p = 2 3: CMOS Transistor Theory CMOS VLSI Design Slide 38
39 CurrentVoltage Relations LongChannel Device Cutoff (V GS V T < 0) no current (not really) Digital Integrated Circuits 2nd Devices
40 I D versus V DS short channel device I D (A) 6 x VGS= 2.5 V Resistive Saturation VGS= 2.0 V V DS = V GS  V T VGS= 1.5 V I D (A) x 10 VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V 1 VGS= 1.0 V 0.5 VGS= 1.0 V V DS (V) Long Channel V DS (V) Short Channel Digital Integrated Circuits 2nd Devices
41 Rabaey s unified model for manual analysis G S D B Digital Integrated Circuits 2nd Devices
42 Transistor Model for Manual Analysis Digital Integrated Circuits 2nd Devices
43 Simple Model versus SPICE 2.5 x 104 V DS =V DSAT Velocity Saturated I D (A) 1 Linear 0.5 V DSAT =V GT V DS =V GT Saturated V DS (V) Digital Integrated Circuits 2nd Devices
44 Even Simpler: The Transistor as a Switch V GS V T R o n S I D D V GS = V DD R mid R 0 V DD /2 V DD V DS Digital Integrated Circuits 2nd Devices
45 The Transistor as a Switch This week s Lab find R eq for our TSMC 180nm process Digital Integrated Circuits 2nd Devices
46 Saturation Effects Discharge of 1pf capacitor, with Vgs of 3,4,5 volts. Also, 12k resistor. d g Which is the resistor? s Digital Integrated Circuits 2nd Devices
47 More on Capacitance q Any two conductors separated by an insulator have capacitance q Gate to channel capacitor is very important Creates channel charge necessary for operation q Source and drain have capacitance to body Across reversebiased diodes Called diffusion capacitance because it is associated with source/drain diffusion 3: CMOS Transistor Theory CMOS VLSI Design Slide 47
48 Gate Capacitance q Approximate channel as connected to source q C gs = ε ox WL/t ox = C ox WL = C permicron W q C permicron is typically about 2 ff/µm polysilicon gate W t ox L n+ n+ ptype body SiO2 gate oxide (good insulator, ε ox = 3.9ε 0 ) 3: CMOS Transistor Theory CMOS VLSI Design Slide 48
49 The Gate Capacitance Polysilicon gate Source n + x d x d W Drain n + L d Top view Gatebulk overlap t ox Gate oxide n + L n + Cross section Digital Integrated Circuits 2nd Devices
50 Dynamic Behavior of MOS Transistor G C GS C GD S D C SB C GB C DB B Digital Integrated Circuits 2nd Devices
51 Physical visualization of FET capacitances Digital Integrated Circuits 2nd Introduction to Circuits, Fourth Edition by Peter Uyemura, Devices Copyright 2004 John Wiley & Sons. All rights reserved.
52 MOS Capacitances Behavior! Digital Integrated Circuits 2nd Devices Copyright 2005 Pearson AddisonWesley. All rights reserved.
53 Gate Capacitance Behavior G G G S C GC C GC C GC D S D S D Cutoff Resistive Saturation Most important regions in digital design: saturation and cutoff Digital Integrated Circuits 2nd Devices
54 Measuring the Gate Cap I V GS Gate Capacitance (F) V GS (V) Digital Integrated Circuits 2nd Devices
55 Diffusion Capacitance q C sb, C db q Undesirable, called parasitic capacitance q Capacitance depends on area and perimeter Use small diffusion nodes Comparable to C g for contacted diff ½ C g for uncontacted Varies with process 3: CMOS Transistor Theory CMOS VLSI Design Slide 55
56 Diffusion Capacitance Channelstop implant N A 1 Side wall W Source N D Bottom x j Side wall L S Substrate N A Channel Digital Integrated Circuits 2nd Devices
57 Calculation of the FET junction capacitance Digital Integrated Circuits 2nd Introduction to Circuits, Fourth Edition by Peter Uyemura, Devices Copyright 2004 John Wiley & Sons. All rights reserved.
58 Capacitances in 0.25 µm CMOS process Values for a Typical Device: Digital Integrated Circuits 2nd Devices
59 Parasitic Resistances G Polysilicon gate L D Drain contact V GS,eff S D W R S R D Drain Digital Integrated Circuits 2nd Devices
60 Final construction of the nfet RC model C G Digital Integrated Circuits 2nd Introduction to Circuits, Fourth Edition by Peter Uyemura, Devices Copyright 2004 John Wiley & Sons. All rights reserved.
61 Latchup V DD V DD p + n + n + p + p + n + R nwell psource nwell R nwell R psubs psubstrate nsource R psubs (a) Origin of latchup (b) Equivalent circuit Digital Integrated Circuits 2nd Devices
62 Summary of MOSFET Operating Regions q Strong Inversion V GS > V T Linear (Resistive) V DS < V DSAT Saturated (Constant Current) V DS V DSAT q Weak Inversion (SubThreshold) V GS V T Exponential in V GS with linear V DS dependence Digital Integrated Circuits 2nd Devices
63 SPICE MODELS Level 1: Long Channel Equations  Very Simple Level 2: Physical Model  Includes Velocity Saturation and Threshold Variations Level 3: SemiEmperical  Based on curve fitting to measured devices Level 4 (BSIM): Emperical  Simple and Popular Digital Integrated Circuits 2nd Devices
64 Main MOS SPICE Parameters Digital Integrated Circuits 2nd Devices
65 SPICE Parameters for Parasitics Digital Integrated Circuits 2nd Devices
66 SPICE Transistors Parameters Digital Integrated Circuits 2nd Devices
67 Circuit Simulation Model of CMOS Inverter Digital Integrated Circuits 2nd Devices
68 Pass Transistors q We have assumed source is grounded q What if source > 0? e.g. pass transistor passing V DD V DD V DD Digital 3: Integrated CMOS Circuits Transistor Theory Slide 68 2nd Devices
69 Pass Transistors q We have assumed source is grounded q What if source > 0? e.g. pass transistor passing V DD V DD V DD q V g = V DD If V s > V DD V t, V gs < V t Hence transistor would turn itself off q nmos pass transistors pull no higher than V DD V tn Called a degraded 1 Approach degraded value slowly (low I ds ) q pmos pass transistors pull no lower than V tp Digital 3: Integrated CMOS Circuits Transistor Theory Slide 69 2nd Devices
70 Pass Transistor Ckts V DD V DD V DD V DD V DD V DD V DD V DD V SS Digital 3: Integrated CMOS Circuits Transistor Theory Slide 70 2nd Devices
71 Pass Transistor Ckts V DD V DD V DD V DD V DD V DD Vs = V DD V tn VDD Vtn VDDVtn V DD V tn V s = V tp V DD V DD V tn V DD V DD 2V tn V SS Digital 3: Integrated CMOS Circuits Transistor Theory Slide 71 2nd Devices
72 Effective Resistance q Shockley models have limited value Not accurate enough for modern transistors Too complicated for much hand analysis q Simplification: treat transistor as resistor Replace I ds (V ds, V gs ) with effective resistance R I ds = V ds /R R averaged across switching of digital gate q Too inaccurate to predict current at any given time But good enough to predict RC delay Digital 3: Integrated CMOS Circuits Transistor Theory Slide 72 2nd Devices
73 RC Delay Model q Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nmos has resistance R, capacitance C Unit pmos has resistance 2R, capacitance C q Capacitance proportional to width q Resistance inversely proportional to width g d k s g R/k kc d s kc kc g d k s g s kc 2R/k kc kc d Digital 3: Integrated CMOS Circuits Transistor Theory Slide 73 2nd Devices
74 RC Values q Capacitance C = C g = C s = C d = 2 ff/µm of gate width Values similar across many processes q Resistance R 6 KΩ*µm in 0.6um process Improves with shorter channel lengths q Unit transistors May refer to minimum contacted device (4/2 λ) Or maybe 1 µm wide device Doesn t matter as long as you are consistent Digital 3: Integrated CMOS Circuits Transistor Theory Slide 74 2nd Devices
75 Inverter Delay Estimate q Estimate the delay of a fanoutof1 inverter A 2 1 Y 2 1 Digital 3: Integrated CMOS Circuits Transistor Theory Slide 75 2nd Devices
76 Inverter Delay Estimate q Estimate the delay of a fanoutof1 2C inverter R A 2 1 Y 2 1 R 2C C Y 2C C C Digital 3: Integrated CMOS Circuits Transistor Theory Slide 76 2nd Devices
77 Inverter Delay Estimate q Estimate the delay of a fanoutof1 2C inverter R A 2 1 Y 2 1 R 2C C Y 2C C R 2C C 2C C C Digital 3: Integrated CMOS Circuits Transistor Theory Slide 77 2nd Devices
78 Inverter Delay Estimate q Estimate the delay of a fanoutof1 2C inverter R A 2 1 Y 2 1 R 2C C Y 2C C R 2C C 2C C C d = 6RC Digital 3: Integrated CMOS Circuits Transistor Theory Slide 78 2nd Devices
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