Step 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since


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1 Step 1. Finding V M Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since V DSn = V M  0 > V M  V Tn V SDp = V DD  V M = (V DD  V M ) V Tp Equate drain currents, omitting the channel length modulation terms (1 λ n V DSn ) and (1 λ p V SDp ) since they tend to cancel out (if λ n = λ p, they exactly cancel out) I Dn = µ n C ox ( 2L V M Ð V Tn) 2 n Ð I Dp = µ p C ox ( 2L p V DD Ð V M V Tp) 2 Letting k n = µ n C ox (/L) n and k p = µ p C ox (/L) p k 2 n ( V M Ð V Tn ) 2 = k p ( V DD Ð V M V Tp ) 2
2 Finding V M (cont.) Result: V M = k p V Tn ( V k DD V Tp ) n k p k n e can set V M = V DD / 2 and achieve a symmetrical transfer curve Example: suppose V Tn =  V Tp = 1 V and V DD = 5 V k p k n V M = = 2.5 k p k n V > k p = k n which makes sense since the transistors must have identical characteristics for the transfer curve to be symmetrical. The mobility of holes in pchannels is about half that of electrons in nchannels, µ p = µ n / 2, which implies that we must adjust the widthlength ratios to compensate: k n = k p > (/L) p = 2(/L) n
3 Step 2. Finding A v s2 v sg2 g mp v sg2 r op _ g1 = g2 d1=d2 v out v in _ v gs1 _ g mn v gs1 r on s1 e note that v sg2 =  v in and can simplify the smallsignal circuit v in v g mn v r on r op g mp v v out
4 Approximate Transfer Curve The smallsignal gain (which is the slope of the transfer curve when the input is equal to the midpoint voltage) is: v out v in = Ð( g mn g mp )( r on r op ) = A v CMOS inverters have a channel length that is as short as possible (to minimize the area... and maximum the density)... the output resistances are relatively small and a typical value is v out / v in =  5 to * The inputlow and inputhigh voltages are: V OUT V OH = V DD A v V DD V M A v V OL = 0 V V IL V M V IH V IN V IL = V M Ð ( V DD ( 2 A v )) V IH = V M ( V DD ( 2 A v ))
5 Noise Margins For k N = k P, the midpoint voltage is V M = 2.5 V. For a slope A v =  5, the inputlow voltage and inputhigh voltages are: V IL = 2.5 V  (1/5) (2.5 V) = 2 V V IH = 2.5 V (1/5) (2.5 V) =3 V The low and high noise margins are therefore: N ML = V IL  V OL = 20 = 2 V N MH = V OH  V IH =53 = 2 V The transition region (or Ògray areaó) is the interval V IL < V IN < V IH or 2 V < V IN < 3 V Finding the actual transfer function requires solving the drain current equations when the pchannel and nchannel are in the appropriate operating regions... and Þnding the transition voltages for the regions. SPICE is good at this job!
6 CMOS Inverter: Propagation Delay The propagation delays t PHL and t PLH are obviously of major importance for digital circuit design... Example: clock frequency = 250 MHz > clock period = 4 ns complex systems (e.g., microprocessor) have around propagation delays per clock period, so we need to have t PLH and t PHL < 100 ps = s Hand calculation of propagation delays: use approximation that input changes instantaneously V IN V OH t CYCLE V OL t V OUT t PHL t PLH VOH V OH V OL 50% t CYCLE t
7 Estimating the Load Capacitance The load capacitance C L consists of C G, the input capacitances of the inverters 2 and 3, and C P, the parasitic capacitance to the substrate from the drain regions of inverter 1 and the interconnections between the output of inverter 1 and the inputs of inverters 2 and 3. V DD L p2 V DD V DD 2 L n2 L p1 V IN V IN 1 V DD C L V OUT L n1 3 L p3 L n3 (a) (b) For hand calculation, we do a worst case estimate of C G by adding the maximum gate capacitances for inverters 2 and 3 C G = C ox [( L) p2 ( L) ( L) n2 p3 ( L) ] n3
8 Parasitic Capacitance from Drain Depletion Regions The drain n and p regions have depletion regions whose stored charge changes during the transient. Take the worst case and use the zerobias depletion capacitance (the maximum, value) as a linear chargestorage element during the transient. active area (thin oxide area) gate contact gate polysilicon gate interconnect contact n polysilicon gate metal interconnect,,,,,,,,,,,,,,,,,, A, source contacts source interconnect L (b) L drain interconnect,,,, bulk contact drain contacts edge of active area L diff
9 Calculation of Parasitic Depletion Capacitance ÒBottomÓ of depletion regions of the load invertersõ drain diffusions contribute a depletion capacitance C BOTT = C Jn ( n L diffn ) C Jp ( p L diffp ) with C Jn and C Jp being the zerobias junction capacitances (ff/µm 2 ) for the n channel MOSFET drainbulk junction and the pchannel MOSFET drainbulk junction, respectively. ÒSidewallÓ of depletion regions of the load invertersõ drain diffusions make an additional contribution: C S = ( n 2L diffn )C JSn ( p 2L diffp )C JSp with C JSn and C JSp being the zerobias sidewall capacitances (ff/µm) for the nchannel MOSFET drainbulk junction and the pchannel MOSFET drainbulk junction, respectively. The total depletion capacitance C DB = C BOTT C S Typical numbers: C JN and C JP are about 0.2 ff/µm 2 and C JSn and C JSp are about 0.5 ff/µm.
10 Parasitic Capacitance from Interconnections ÒiresÓ consist of metal lines connecting the output of the inverter to the input of the next stage. In cross section, polysilicon gate,, metal interconnect (width m, length L m ),,,, 0.6 µm deposited oxide 0.5 µm thermal oxide p p (grounded) gate oxide The p layer (i.e., heavily doped with acceptors) under the thick thermal oxide (500 nm = 0.5 µm) and deposited oxide (600 nm = 0.6 µm) depletes only slightly when positive voltages appear on the metal line, so the capacitance is approximately the oxide capacitance: C IRE = C thickox ( m L m ) where the oxide thickness = 500 nm 600 nm = 1.1 µm. * For large digital systems, the parasitic interconnect capacitance can dominate the load capacitance  C L = C G C P = C G (C DB C IRE )
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