Digital Microelectronic Circuits ( ) Ratioed Logic. Lecture 8: Presented by: Mr. Adam Teman

Transcription

1 Digital Microelectronic ircuits ( ) Presented by: Mr. Adam Teman Lecture 8: atioed Logic 1

2 Motivation In the previous lecture, we learned about Standard MOS Digital Logic design. MOS is unquestionably the leading design family in use today, do to its many advantages and relative simplicity. However, it has a number of drawbacks that have led to the development of alternative solutions. The main drawback of Standard MOS is its relatively large area (2N transistors to implement an N-input gate). In this lecture, we will start to overview a number of alternative logic families that try to reduce the number of transistors needed to implement a logic function. 2

3 What will we learn today? 8.1 atioed Logic 8.2 Pseudo NMOS 8.3 LE of Pseudo NMOS 3

4 atioed Logic 8.2 Pseudo NMOS 8.3 LE of Pseudo NMOS Let s start with an important concept that has driven a number of logic families: ATIOED LOGI 4

5 atioed Logic oncept When we discussed Standard MOS during the previous two lectures, we spent quite a while analyzing the sizes of the transistors. It is important to note that these sizing considerations improved the performance (=speed) of the logic gates, but not their functionality. In other words, even if we implemented the gates without size considerations, we would arrive at the requested logic function (though it might take a while ). 5

6 atioed Logic oncept atioed Logic is an attempt to reduce the number of transistors required to implement a given logic function, waiving the assurance of functionality. As its name implies, in order to ensure functionality, a certain ratio of sizes has to be kept between various devices that make up the gate. atioed Logic has another great disadvantage high static power dissipation which makes it vary scarcely used. But the concept is implemented in quite a few complex circuits (such as memory circuits), and so it is important to understand. 6

7 atioed Logic oncept The concept of atioed Logic uses the same Pull Down Network as MOS, but uses a simple Load as its Pull Up Network. This Load constantly leaks current from the supply to the output capacitance. In this way, the output is charged when the PDN is closed, providing a 1. On the other hand, the Load s resistance is much larger than that of an open PDN, so when the PDN is open, the output is pulled down to V OL. The ratio between the resistance of the Load and the PDN is crucial in designing such a gate, hence it is called atioed Logic. 7

8 VT of Generic atioed Logic Gate 8

9 atioed Logic haracteristics N transistors + Load V DD V V OL OH V PDN DD PDN L esistive Load L Asymmetrical esponse F Static Power onsumption In 1 In 2 PDN Slow pull up: t 0.69 plh out L In 3 V SS 9

10 Load Implementation Early atioed Logic designs used a simple resistor as the Load. This approach had several drawbacks, especially with the difficulty in resistor implementation in VLSI. 10

11 Load Implementation Accordingly, the Load was replaced with a Diode-connected nmos (V GD =0) a.k.a. Saturated Load Inverter. This circuit stopped conducting at V GS =V DD -V Tn (weak 1 ) providing a largely reduced swing. 11

12 Load Implementation To improve the swing, the nmos (also known as an enhancement mode nmos) was replaced with a Depletion Mode nmos. This is a special, highly doped nmos with a negative threshold voltage (V Tn <0). This was used for some time until the Pseudo nmos inverter was invented, replacing the nmos load with a pmos connected to ground. 12

13 atioed Logic 8.2 Pseudo NMOS 8.3 LE of Pseudo NMOS The only really surviving ratioed logic family is: PSEUDO NMOS 13

14 Pseudo nmos The topology of a Pseudo nmos gate is shown in the following figure: The clear advantage of this gate over Standard MOS is the reduced number of transistors:» N+1 transistors to implement an N-input gate. 14

15 Pseudo nmos Using a pmos in the PUN, we get a Strong 1 when the PDN is closed, so V OHmax =V DD. On the other hand, when the PDN is open, there is a fight between the PDN and the pmos load. 15

16 Pseudo nmos To calculate V OLmin, we will equate the pmos saturation current with the PDN current, assuming that it consists of nmos devices in Linear Mode. We will mark the drive strength of the PDN as k neq and assume short channel devices*: 2 V 1 2 Dp p DD Tp DSAT Dn neq DD Tn OL OL DSAT I k V V V I k V V V V 2 2 *alculate for long channel devices at home! 16

17 Pseudo nmos Making a few minor assumptions, we arrive at: V OL k p VDD VTp VDSAT p Wp V k V V W neq DD Tn n neq DSAT So to get a Low V OLmin, we need the pmos to be much smaller than the equivalent width of the nmos network. Making the pmos small means a small charge current, resulting in a large t plh! 17

18 Pseudo nmos In addition, we get static power dissipation from the direct path between V DD and GND when outputting a 0 : V Plow VDDI low VDDk p VDD VTp VDSAT 2 DSAT 2 Accordingly, Pseudo nmos won t usually be used in low power or high frequency applications. 18

19 Pseudo nmos However, when large fan-in gates are needed, the reduced transistor count can be attractive. 19

20 VT of Pseudo NMOS 20

21 Pseudo NMOS haracteristics Summary Small β ratio (small pmos, big PDN):» Lower VOL» Better Gain» Less static power» Fast t phl But» Slow t plh» Bigger capacitive load In general:» N+1 Transistors» Only 1 NMOS load to previous stage» Make sure PMOS resistance at least 4 x PDN 21

22 atioed Logic 8.2 Pseudo NMOS 8.3 LE of Pseudo NMOS Now we can compare this logic family using our previously developed design methodology: LOGIAL EFFOT OF PSEUDO NMOS 22

23 Pseudo-NMOS ising Edge t plh is simply through the pmos: t 0.69 plh L p,min Let s look at the Logical Effort parameters of this transition: eq p,min W min W min 1 G n g min A βw min 1 min d n d 23

24 ising Edge Logical Effort Now it is straightforward to calculate the LE parameters. eq p,min G n g min d n d min 1 p p,min n dmin n p,min 2 3dmin p,min ndmin 2 LE n p,min dmin p LE 1 gate inv gate inv W min d, gate d,min g, gate g,min for =1: 4 2 n p LE for =4: 10 8 n p LE

25 But what about t phl? Pseudo-NMOS Falling Edge» Let s find the Thevenin Equivalent: V N Thevenin V DD N P Thevenin N N P P» So we would expect: t 0.69 phl L Thevenin» But the swing is V DD /2, not V Thevenin /2» So it actually takes a bit longer to discharge. 25

26 esponse on Falling edge The smaller PUN :» The smaller the swing, so it takes less time to reach 0.5(V OH -V OL )» But the longer it takes to reach 0.5V DD! 26

27 Falling Edge Logical Effort t phl presents a new problem:» Both the PUN and PDN are conducting. thevenin n p I PUN I PDN 1 I PDN -I PUN So eq is smaller than n? How could this be the pmos is fighting the discharge It s because of the swing 27

28 Pseudo nmos Logical Effort What is the actual?» Available urrent is the difference between PDN and PUN.» The current is approximately proportional to the resistance. I PUN VDD VDD V DD eq PDN PUN n,min eq n,min 1 eq p,min n 2 n for =1: 2 for =4: n eq n,min n eq n,min 3.5 n,min n I PDN 1 I PDN -I PUN So eq is bigger than n? That makes more sense 28

29 Pseudo nmos Logical Effort So the parameters for pull down: eq n nmin 1 2 G n g min d n d min 1 p LE n d,min p nmin n n 0.5 n min 3d,min 3 n 0.5 nmin n g,min LE n nmin g,min n n gate inv gate inv d, gate d,min g, gate g,min for =1: 4 2 n p LE 3 3 for =4: 10 8 n p LE I PUN I PDN 1 I PDN -I PUN 29

30 Pseudo nmos Logical Effort - Summary So to summarize:» With β=1 (high V OL ), we got: t plh : p LE t : 3 3 phl p LE 3 3» Our LE is LOWE than an inverter!» But don t forget we have depleted noise margins and we have static power» With β=4 (more realistic), we got: t plh : p LE t : 3 3 phl p LE 21 21» Our HL transition has much better performance than MOS!» But the LH transition is much worse. 30

31 Last Lecture Pseudo NMOS 31

32 Last Lecture ising Edge (easy): 32

33 Last Lecture Falling Edge ( complicated ): 33

34 Another Example What if we were to give the pmos a long L?» Say we want β=4, so we would choose W p /L p =W min /4 Lmin g gmin d 2 dmin 4 8 eqlh P eq p I I I 7 I eqhl I 7 HL n eq eq eq LH : p LH LE 3 3 LH HL : p 8 HL LE HL W 4L W L min min min min I PUN I PDN 1 I PDN -I PUN 34