EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing

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1 EE115C Winter 2017 Digital Electronic Circuits Lecture 3: MOS RC Model, CMOS Manufacturing

2 Agenda MOS Transistor: RC Model (pp ) S R on D CMOS Manufacturing Process (pp ) S S C GS G G C GD D D C SB C GB C DB B EE115C Winter

3 Switch Model of CMOS Transistor V GS G NMOS: V GS > 0 PMOS: V GS < 0 S D S R on D S V GS < V T V GS > V T D EE115C Winter

4 The Transistor as a Switch MOS can be treated as equivalent resistance Calculating MOS resistance: S V GS V T R on D I D R mid V GS = V DD R 0 good approximation (I-V linear) V DD /2 V DD V DS This model will be used for delay analysis EE115C Winter

5 Computing Equivalent Resistance (1/2) Method 1 ( exact ): by integration EE115C Winter

6 Computing Equivalent Resistance (2/2) Method 2: simple averaging The averaging works because of approximately linear dependence of I DS on V DS (recall the CLM model) Use this formula for hand analysis EE115C Winter

7 R eq (Ohm) R on vs. V DD (Simulation Result) R on increases rapidly as V DD approaches V T 7 x W/L=1, L=0.25 m V DD (V) EE115C Winter

8 MOS Capacitances G C GS C GD S D C SB C GB C DB B EE115C Winter

9 The Gate Capacitance Polysilicon gate Source n + x d x d W Drain n + L d Top view Gate-bulk overlap C gate t ox ox WL Gate oxide t ox n + L n + Cross section EE115C Winter

10 Capacitance Components #1: Gate-Channel Capacitance #2: Gate Overlap Capacitance #3: Junction/Diffusion Capacitance EE115C Winter

11 #1: Gate-Channel Capacitance G G G S C GC C GC C GC D S D S D Cut-off Resistive Saturation C GCB C GCS C GCD Textbook: page 109 Most important regions in digital design: saturation and cut-off EE115C Winter

12 A Close Look at Gate-Channel Capacitance C GC WLC ox WLC ox C GC WLC ox 2 C GCB C GCS =C GCD WLC ox 2 C GCS C GCD 2WLC ox 3 V GS 0 1 V DS / (V GS V T ) C gate as a function of V GS (with V DS = 0) C gate as a function of the degree of saturation EE115C Winter

13 Summary: #1: Gate-Channel Capacitance G G G C GC C GC C GC S D S D S D Cut-off Resistive Saturation C GCB C GCS C GCD Textbook: page 109 Off/Lin C gate = C ox W L eff ox Cox Sat C gate = (2/3) C ox W L eff tox EE115C Winter

14 Source #2: Gate Overlap Capacitance n + x d x d W Drain n + Polysilicon gate L d Top view Gate-bulk overlap Gate oxide Source n + x d L d Top view x d W Drain n + Gate-bulk overlap t ox n + L n + Cross section C O C ox x d Gate oxide t ox n + L n + Off/Lin/Sat C GSO = C GDO = C O W Cross section EE115C Winter

15 Capacitance (F) Measuring the Gate Cap Transient analysis 10 9 x V GS 7 I Gate Capacitance (F) V GS (V) EE115C Winter

16 Finding Equivalent Capacitance Delay Curve fitting approach to find a number that works for hand analysis of the gate delay Understand the limitations: the model will depend on signal rise times, voltage, temperature, process parameter variation t p1 t p2 c gate Experiment: find C gate to match propagation delays t p1 = t p2 C gate is equivalent cap of the green gate EE115C Winter

17 #3: Diffusion Capacitance Channel-stop implant N A + W Bottom Side wall Source N D x j Side wall L S Channel Substrate N A C diff = C bottom + C sw = C j AREA + C jsw PERIMETER = C j L S W + C jsw (2L S + W) EE115C Winter

18 #3: Diffusion Capacitance Channel-stop implant N A + W Bottom Side wall Source N D x j Side wall L S Channel Substrate N A C diff = C bottom + C sw = C j AREA + C jsw PERIMETER Off/Lin/Sat C diff = C j L S W + C jsw (2L S +W) EE115C Winter

19 Junction Capacitance is Bias-dependent C j C j0 (1 V ) D 0 m m = 0.5: abrupt junction m = 0.33: linear junction EE115C Winter

20 #3 Diffusion Capacitance: Summary of Equations Bottom-plate C Side-wall C m = 0.5: abrupt junction m = 0.33: linear junction EE115C Winter

21 Linearizing the Junction Cap Replace non-linear capacitance by large-signal equivalent linear capacitance, which displaces equal charge over voltage swing of interest Typical value for K eq around 0.5 EE115C Winter

22 Summary: Capacitive Device Model Gate-Channel Capacitance C GC = C ox W L eff (Off, Linear) C GC = (2/3) C ox W L eff (Saturation) Circuit design C gate Gate Overlap Capacitance C GSO = C GDO = C O W (Always) Junction/Diffusion Capacitance C diff = C j L S W + C jsw (2L S + W) (Always) C parasitic Zero-bias C diff > C gate MOS On C diff C gate EE115C Winter

23 Outline MOS Transistor: RC Model (pp ) CMOS Manufacturing Process (pp ) EE115C Winter

24 Photo-Lithographic Process oxidation optical mask photoresist removal (ashing) photoresist coating stepper exposure process step Typical operations in a single photolithographic cycle (from [Fullman]). spin, rinse, dry acid etch photoresist development EE115C Winter

25 Patterning of SiO 2 Si-substrate (a) Silicon base material Si-substrate (b) After oxidation and deposition of negative photoresist Si-substrate (c) Stepper exposure Photoresist SiO 2 UV-light Patterned optical mask Exposed resist Si-substrate Si-substrate Si-substrate Hardened resist SiO 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 (e) After etching Chemical or plasma etch Hardened resist SiO 2 SiO 2 (f) Final result after removal of resist EE115C Winter

26 CMOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers EE115C Winter

27 CMOS Process Walk-Through p-epi p+ (a) Base material: p+ substrate with p-epi layer p-epi p+ SiN 3 4 SiO 2 (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer) p+ (c) After plasma etch of insulating trenches using the inverse of the active area mask EE115C Winter

28 CMOS Process Walk-Through SiO 2 (d) After trench filling, CMP planarization, and removal of sacrificial nitride n (e) After n-well and V TP adjust implants p (f) After p-well and V TN adjust implants EE115C Winter

29 CMOS Process Walk-Through poly(silicon) (g) After polysilicon deposition and etch n+ p+ (h) After n+ source/drain and p+ source/drain implants. These steps also dope the polysilicon. SiO 2 (i) After deposition of SiO 2 insulator and contact hole etch. EE115C Winter

30 CMOS Process Walk-Through Al (j) After deposition and patterning of first Al layer. Al SiO 2 (k) After deposition of SiO 2 insulator, etching of via s, deposition and patterning of second layer of Al. EE115C Winter

31 Advanced Metalization EE115C Winter