EE5780 Advanced VLSI CAD


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1 EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1
2 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 4.
3 Activity 1) If the width of a transistor increases, the current will increase decrease not change ) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change 4.3
4 Activity 1) If the width of a transistor increases, the current will increase decrease not change ) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change 4.4
5 Pass Transistors We have assumed source is grounded What if source > 0? e.g. pass transistor passing V g = If V s > V t, V gs < V t Hence transistor would turn itself off NMOS pass transistors pull no higher than V tn Called a degraded 1 Approach degraded value slowly (low I ds ) PMOS pass transistors pull no lower than V tp 4.5
6 Pass Transistor Ckts Vs = V tn VDD Vtn VDDVtn V tn V SS V s = V tp V tn V tn 4.6
7 DC Response DC Response: V out vs. V in for a gate Ex: Inverter When V in = 0 > V out = When V in = > V out = 0 In between, V out depends on transistor size and current By KCL, must settle such that I dsn = I dsp We could solve equations V in But graphical solution gives more insight I dsp I dsn V out 4.7
8 Transistor Operation Current depends on region of transistor behavior For what V in and V out are NMOS and PMOS in Cutoff? Linear? Saturation? 4.8
9 NMOS Operation Cutoff Linear Saturated V gsn < V tn V gsn > V tn V gsn > V tn V dsn < V gsn V tn V dsn > V gsn V tn V in I dsp I dsn V out 4.9
10 NMOS Operation Cutoff Linear Saturated V gsn < V tn V gsn > V tn V gsn > V tn V dsn < V gsn V tn V dsn > V gsn V tn V gsn = V in V dsn = V out V in I dsp I dsn V out 4.10
11 NMOS Operation Cutoff Linear Saturated V gsn < V tn V in < V tn V gsn > V tn V in > V tn V dsn < V gsn V tn V out < V in V tn V gsn > V tn V in > V tn V dsn > V gsn V tn V out > V in V tn V gsn = V in I dsp V dsn = V out V in I dsn V out 4.11
12 PMOS Operation Cutoff Linear Saturated V gsp > V gsp < V gsp < V dsp > V dsp < V in I dsp I dsn V out 4.1
13 PMOS Operation Cutoff Linear Saturated V gsp > V tp V gsp < V tp V gsp < V tp V dsp > V gsp V tp V dsp < V gsp V tp V in I dsp I dsn V out 4.13
14 PMOS Operation Cutoff Linear Saturated V gsp > V tp V gsp < V tp V gsp < V tp V dsp > V gsp V tp V dsp < V gsp V tp V gsp = V in  V tp < 0 V dsp = V out  V in I dsp I dsn V out 4.14
15 PMOS Operation Cutoff Linear Saturated V gsp > V tp V in > + V tp V gsp < V tp V in < + V tp V dsp > V gsp V tp V out > V in V tp V gsp < V tp V in < + V tp V dsp < V gsp V tp V out < V in V tp V gsp = V in  V tp < 0 V dsp = V out  V in I dsp I dsn V out 4.15
16 IV Characteristics Make PMOS wider than NMOS such that n = p V gsn5 I dsn V gsn4 V gsn3 V dsp V gsp1 V gsp  0 V gsn V gsn1 V gsp3 V dsn V gsp4 I dsp V gsp5 4.16
17 Current vs. V out, V in V in0 V in5 I dsn, I dsp V in1 V in4 V in V in3 V in3 V in4 V in V in1 V out 4.17
18 For a given V in : Load Line Analysis Plot I dsn, I dsp vs. V out V out must be where currents are equal V in0 V in5 I dsn, I dsp V in1 V in4 V in I dsp V out I dsn V in V in3 V in3 V in4 V in V in1 V out 4.18
19 Load Line Analysis V in = 0 V in0 I dsn, I dsp V in0 V out 4.19
20 Load Line Analysis V in = 0. I dsn, I dsp V in1 V in1 V out 4.0
21 Load Line Analysis V in = 0.4 I dsn, I dsp V in V in V out 4.1
22 Load Line Analysis V in = 0.6 I dsn, I dsp V in3 V in3 V out 4.
23 Load Line Analysis V in = 0.8 I dsn, I dsp V in4 V in4 V out 4.3
24 Load Line Analysis V in = V in0 V in5 I dsn, I dsp V in1 V in V in3 V in4 V out 4.4
25 Load Line Summary 4.5
26 DC Transfer Curve Transcribe points onto V in vs. V out plot V in0 V in5 A B V in1 V in4 V out C V in V in3 V in3 V in4 V out V in V in1 0 D E V tn / +V tp V in 4.6
27 Operating Regions Revisit transistor operating regions Region NMOS PMOS A Cutoff Linear B Saturation Linear C Saturation Saturation D Linear Saturation E Linear Cutoff V out A B 0 C D E V tn / +V tp V in 4.7
28 Beta Ratio If p / n 1, switching point will move from / Called skewed gate Other gates: collapse into equivalent inverter V out p 0.1 n p n V in 4.8
29 Noise Margins How much noise can a gate input see before it does not recognize the input? Logical High Output Range Output Characteristics V OH NM H Input Characteristics Logical High Input Range V IH V IL Indeterminate Region Logical Low Output Range V OL NM L GND Logical Low Input Range 4.9
30 Logic Levels To maximize noise margins, select logic levels at unity gain point of DC transfer characteristic V out Unity Gain Points Slope = 1 V OH p / n > 1 V in V out V OL 0 V tn V IL V IH  V tp V in 4.30
31 Transient Response DC analysis tells us V out if V in is constant Transient analysis tells us V out (t) if V in (t) changes Requires solving differential equations Input is usually considered to be a step or ramp From 0 to or vice versa 4.31
32 Inverter Step Response Ex: find step response of inverter driving load cap V V in out () t ( t t ) dvout () t dt ut ( t) V 0 0 DD V in (t) I dsn (t) V out (t) C load 4.3
33 Inverter Step Response Ex: find step response of inverter driving load cap V V in out ( t) ut ( t0) V ( t t ) V dvot u dt ( t) 0 DD DD V in (t) I dsn (t) V out (t) C load 4.33
34 Inverter Step Response Ex: find step response of inverter driving load cap V V in out () t ut ( ( t t ) dvo ut ( t) dt 0 t) V 0 V I C DD dsn DD () t load V in (t) I dsn (t) V out (t) C load t t I t V V V V V 0 dsn () Vout DD t out DD t 4.34
35 Inverter Step Response Ex: find step response of inverter driving load cap I V V in out () t ut ( ( t t ) 0 dvo ut ( t) dt t) V 0 V I DD dsn C DD () t load 0 t t dsn ( t) VDD V Vout VDD Vt Vout ( t) VDD V t V () t V V D V out out D t 0 V in (t) I dsn (t) V out (t) C load 4.35
36 Inverter Step Response Ex: find step response of inverter driving load cap V V in out () t ut ( ( t t ) dvo ut ( t) dt 0 t) V 0 V I C DD dsn DD () t load V in (t) I dsn (t) V out (t) C load I 0 t t dsn ( t) VDD V Vout VDD Vt Vout ( t) VDD V t V () t V V D V out out D t 0 t 0 V in (t) V out (t) t 4.36
37 Delay Definitions t pdr : rising propagation delay From input to rising output crossing / t pdf : falling propagation delay From input to falling output crossing / t pd : average propagation delay t pd = (t pdr + t pdf )/ t r : rise time From output crossing 0. to 0.8 t f : fall time From output crossing 0.8 to
38 Delay Definitions t cdr : rising contamination delay From input to rising output crossing / t cdf : falling contamination delay From input to falling output crossing / t cd : average contamination delay t pd = (t cdr + t cdf )/ 4.38
39 Simulated Inverter Delay Solving differential equations by hand is too hard SPICE simulator solves the equations numerically Uses more accurate IV models too! But simulations take time to write (V) V in t pdf = 66ps t pdr = 83ps 0.5 V out p 400p 600p 800p 1n t(s)
40 Delay Estimation We would like to be able to easily estimate delay Not as accurate as simulation But easier to ask What if? The step response usually looks like a 1 st order RC response with a decaying exponential. Use RC delay models to estimate delay C = total capacitance on output node Use effective resistance R So that t pd = RC Characterize transistors by finding their effective R Depends on average current as gate switches 4.40
41 Effective Resistance Shockley models have limited value Not accurate enough for modern transistors Too complicated for much hand analysis Simplification: treat transistor as resistor Replace I ds (V ds, V gs ) with effective resistance R I ds = V ds /R R averaged across switching of digital gate Too inaccurate to predict current at any given time But good enough to predict RC delay 4.41
42 RC Delay Model Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit NMOS has resistance R, capacitance C Unit PMOS has resistance R, capacitance C Capacitance proportional to width Resistance inversely proportional to width g d k s g d R/k kc s kc kc g d k s g s kc R/k kc kc d 4.4
43 Capacitance RC Values C = C g = C s = C d = ff/m of gate width Values similar across many processes Resistance R 6 K*m in 0.6um process Improves with shorter channel lengths Unit transistors May refer to minimum contacted device (4/ ) Or maybe 1 m wide device Doesn t matter as long as you are consistent 4.43
44 Inverter Delay Estimate Estimate the delay of a fanoutof1 inverter R C A 1 Y 1 R C C Y C C R C C C C C Delay = 6RC 4.44
45 Delay Model Comparison 4.45
46 Example: 3input NAND Sketch a 3input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R)
47 3input NAND Caps Annotate the 3input NAND gate with gate and diffusion capacitance
48 3input NAND Caps Annotate the 3input NAND gate with gate and diffusion capacitance. C C C C C C C C C 3C 3C 3C C 3C 3C 3C 4.48
49 3input NAND Caps Annotate the 3input NAND gate with gate and diffusion capacitance. 5C 5C 5C C 3C 3C 4.49
50 Elmore Delay 1v R C V(t) t Vt () 1e RC Time Constant=RC What is the time constant for more complex circuits? A B C Inv 1 Inv 4.50
51 Elmore Delay (Cont.) ON transistors look like resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder t R C pd itosource i nodes i R C R R C... R R... R C R 1 R R 3 R N N N C 1 C C 3 C N 4.51
52 Elmore Delay (Cont d) Resistanceoriented Formula: Tdelay RiCdownstream, i i on path T delay,4 =R 1 (C 1 +C +C 3 +C 4 +C 5 )+R (C +C 4 +C 5 )+R 4 C 4 4.5
53 Example: input NAND Estimate worstcase rising and falling delay of  input NAND driving h identical gates. Y A B x h copies 4.53
54 Example: input NAND Estimate rising and falling propagation delays of a input NAND driving h identical gates. A B x 6C C Y 4hC h copies 4.54
55 Example: input NAND Estimate rising and falling propagation delays of a input NAND driving h identical gates. A B x 6C C Y 4hC h copies Rising Delay R Y (6+4h)C tpdr 64h RC 4.55
56 Example: input NAND Estimate rising and falling propagation delays of a input NAND driving h identical gates. A B x 6C C Y 4hC h copies Falling Delay R/ x R/ C Y (6+4h)C R 6 4 R R 7 4 tpdf C h C h RC 4.56
57 Delay has two parts Delay Components Parasitic delay 6 or 7 RC Independent of load Effort delay 4h RC Proportional to load capacitance 4.57
58 Contamination Delay Bestcase (contamination) delay can be substantially less than propagation delay. Ex: If both inputs fall simultaneously A B x 6C C Y 4hC R R Y (6+4h)C tcdr 3h RC 4.58
59 Diffusion Capacitance We assumed contacted diffusion on every s / d. Good layout minimizes diffusion area Ex: NAND3 layout shares one diffusion contact Reduces output capacitance by C Merged uncontacted diffusion might help too Shared Contacted Diffusion Merged Uncontacted Diffusion C C Isolated Contacted Diffusion 3 3 7C 3C 3C 3C 3C 3 3C 4.59
60 Layout Comparison Which layout is better? A B A B Y Y GND GND 4.60
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