Lecture 14  Digital Circuits (III) CMOS. April 1, 2003


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1 Microelectronic Devices and Circuits  Spring 23 Lecture 141 Lecture 14  Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter: noise margins 3. CMOS inverter: propagation delay Reading assignment: Howe and Sodini, Ch. 5, 5.4 Announcements: Final exam: May 23, 1:34:3 (Walker) HSPICE tutorial by Susan Luschas: April 1, 7:39:3 (Rm ) Webcast of Lecture 13 available (see course website)
2 Microelectronic Devices and Circuits  Spring 23 Lecture 142 How does CMOS work? Key questions What is special about CMOS as a logic technology? What are the key design parameters of a CMOS inverter? How can one estimate the propagation delay of a CMOS inverter?
3 Microelectronic Devices and Circuits  Spring 23 Lecture 143 Screen shots of NMOS inverters (currently in WebLab): NMOS inverter with resistor pullup Main problem: slow pull up
4 Microelectronic Devices and Circuits  Spring 23 Lecture 144 NMOS inverter with current source pullup Main problem: DC current in one logic state
5 Microelectronic Devices and Circuits  Spring 23 Lecture Complementary MOS (CMOS) Inverter Circuit schematic: V IN C L Basic operation: V IN = = V GSn =<V Tn NMOS OFF V SGp = > V Tp PMOS ON V IN = = V GSn = >V Tn NMOS ON V SGp =< V Tp PMOS OFF
6 Microelectronic Devices and Circuits  Spring 23 Lecture 146 Output characteristics of both transistors: I Dn I Dp V GSn V SGp V GSn =V Tn V SGp =V Tp V DSn V SDp Note: V IN = V GSn = V SGp V SGp = V IN = V DSn = V SDp V SDp = I Dn = I Dp Combine into single diagram of I D vs. with V IN as parameter.
7 Microelectronic Devices and Circuits  Spring 23 Lecture 147 I D V IN V IN V IN C L no current while idling in any logic state. Transfer function: NMOS cutoff PMOS triode NMOS saturation PMOS triode NMOS saturation PMOS saturation NMOS triode PMOS saturation NMOS triode PMOS cutoff V Tn +V Tp V IN railtorail logic: logic levels are and high A v around logic threshold good noise margins
8 Microelectronic Devices and Circuits  Spring 23 Lecture 148 Transfer characteristics of CMOS inverter in WebLab:
9 Microelectronic Devices and Circuits  Spring 23 Lecture CMOS inverter: noise margins NM L V M A v (V M ) V IL V M V IH V IN NM H Calculate V M Calculate A v (V M ) Calculate NM L and NM H Calculate V M (V M = V IN = ) At V M both transistors saturated: I Dn = 1 W n µ n C ox (V M V Tn ) 2 2 L n I Dp = 1 W p µ p C ox ( V M + V Tp ) 2 2 L p
10 Microelectronic Devices and Circuits  Spring 23 Lecture 141 Define: k n = W n L n µ n C ox, k p = W p L p µ p C ox Since: I Dn = I Dp Then: 1 2 k n(v M V Tn ) 2 = 1 2 k p( V M + V Tp ) 2 Solve for V M : V M = V Tn + k p k n ( + V Tp ) 1+ k p k n Usually, V Tn and V Tp fixed and V Tn = V Tp V M engineered through k p /k n ratio
11 Microelectronic Devices and Circuits  Spring 23 Lecture Symmetric case: k n = k p This implies: V M = 2 k p k n =1= W p L p µ p C ox W n L n µ n C ox W p L p µ p W n W p 2 W n L n 2µ p L p L n Since usually L p L n W p 2W n. Asymmetric case: k n k p,or W n L n W p L p V M V Tn NMOS turns on as soon as V IN goes above V Tn. Asymmetric case: k n k p,or W n L n W p L p V M + V Tp PMOS turns on as soon as V IN goes below + V Tp. Can engineer V M anywhere between V Tn and + V Tp.
12 Microelectronic Devices and Circuits  Spring 23 Lecture Calculate A v (V M ) Smallsignal model: + S2 V IN C L + + v sg2 =v in g mp v sg2 r op  G2 D2 + D1 G1 v in v gs1 g mn v gs1 r on v out S1 G1=G2 D1=D2 + + v in gmn v in g mp v in r on //r op v out   S1=S2 This can be rather large. A v = (g mn + g mp )(r on //r op )
13 Microelectronic Devices and Circuits  Spring 23 Lecture Noise margins NM L V M A v (V M ) V IL V M V IH V IN NM H Noisemarginlow: Therefore: V IL = V M V M A v NM L = V IL V OL = V IL = V M V M A v In the limit of A v : NM L V M
14 Microelectronic Devices and Circuits  Spring 23 Lecture Noisemarginhigh: NM L V M A v (V M ) V IL V M V IH V IN NM H and V IH = V M (1 + 1 A v ) NM H = V OH V IH = V M (1 + 1 A v ) In the limit of A v : NM H V M
15 Microelectronic Devices and Circuits  Spring 23 Lecture CMOS inverter: propagation delay Inverter propagation delay: time delay between input and output signals; key figure of merit of logic speed. Typical propagation delays: < 1 ns. Complex logic system has 25 propagation delays per clock cycle. Estimation of t p : use squarewave at input V IN t CYCLE t t PHL t PLH 5% t CYCLE t Average propagation delay: t p = 1 2 (t PHL + t PLH )
16 Microelectronic Devices and Circuits  Spring 23 Lecture Propagation delay hightolow: V IN : LO HI : HI LO C L V IN = = V IN = = V IN = VOUT = C L C L C L t= t=+ t During early phases of discharge, NMOS is saturated and PMOS is cutoff. Time to discharge half of C L : t PHL 1 2 charge of C = discharge current
17 Microelectronic Devices and Circuits  Spring 23 Lecture Charge in C L at t = : Q L (t = )=C L Discharge current (NMOS in saturation): Then: I Dn = W n 2L n µ n C ox ( V Tn ) 2 t PHL C L W n L n µ n C ox ( V Tn ) 2 I D V IN V IN
18 Microelectronic Devices and Circuits  Spring 23 Lecture Propagation delay lowtohigh: V IN : HI LO : LO HI C L V IN = = C L V IN = = C L V IN = C L = t= t=+ t During early phases of charge, PMOS is saturated and NMOS is cutoff. Time to charge half of C L : t PLH 1 2 charge of C = charge current
19 Microelectronic Devices and Circuits  Spring 23 Lecture Charge in C L at t = : Q L (t = ) =C L Charge current (PMOS in saturation): Then: I Dp = W p 2L p µ p C ox ( + V Tp ) 2 t PLH C L W p L p µ p C ox ( + V Tp ) 2 I D V IN V IN
20 Microelectronic Devices and Circuits  Spring 23 Lecture 142 Key dependencies of propagation delays: t p Reason: Q(C L ), but also I D Tradeoff:, more power usage. L t p Reason: L I D Tradeoff: manufacturing costs!
21 Microelectronic Devices and Circuits  Spring 23 Lecture Components of load capacitance C L : following logic gates: must add capacitance presented by each gate of every transistor the output is connected to interconnect wire that connects output to input of following logic gates own draintobody capacitances C L = C G + C wire + C DBn + C DBp V IN C wire [See details in Howe & Sodini 5.4.3]
22 Microelectronic Devices and Circuits  Spring 23 Lecture Key conclusions Key features of CMOS inverter: no current while idling in any logic state railtorail logic: logic levels are and high A v around logic threshold good noise margins CMOS inverter logic threshold and noise margins engineered through W n /L n and W p /L p. Key dependences of propagation delay: t p L t p
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