CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
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1 CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
2 Review: Design Abstraction Levels SYSTEM + MODULE GATE CIRCUIT V in V out S n+ G DEVICE D n+ CMPEN 411 L03 S.2
3 The NMOS Transistor Cross Section n areas have been doped with donor ions (arsenic) of concentration N D - electrons are the majority carriers Source n+ W Polysilicon Gate L Gate oxide Drain n+ Field-Oxide (SiO 2 ) p substrate Bulk (Body) p areas have been doped with acceptor ions (boron) of concentration N A - holes are the majority carriers CMPEN 411 L03 S.3
4 The MOS Transistor Polysilicon Aluminum CMPEN 411 L03 S.4
5 Switch Model of NMOS Transistor V GS Gate Source (of carriers) Drain (of carriers) Open (off) (Gate = 0 ) Closed (on) (Gate = 1 ) R on V GS < V T V GS > V T CMPEN 411 L03 S.5
6 Switch Model of PMOS Transistor V GS Gate Source (of carriers) Drain (of carriers) Open (off) (Gate = 1 ) Closed (on) (Gate = 0 ) R on V GS > V DD V T V GS < V DD V T CMPEN 411 L03 S.6
7 Threshold Voltage Concept S V GS + - G D n+ n+ n channel p substrate depletion region B The value of V GS where strong inversion occurs is called the threshold voltage, V T CMPEN 411 L03 S.7
8 The Threshold Voltage where V T = V T0 + ( -2 F + V SB - -2 F ) V T0 is the threshold voltage at V SB = 0 and is mostly a function of the manufacturing process CMPEN 411 L03 S.8 Difference in work-function between gate and substrate material, oxide thickness, Fermi voltage, charge of impurities trapped at the surface, dosage of implanted ions, etc. V SB is the source-bulk voltage F = - T ln(n A /n i ) is the Fermi potential ( T = kt/q = 26mV at 300K is the thermal voltage; N A is the acceptor ion concentration; n i 1.5x10 10 cm -3 at 300K is the intrinsic carrier concentration in pure silicon) = (2q si N A )/C ox is the body-effect coefficient (impact of changes in V SB ) ( si =1.053x10-10 F/m is the permittivity of silicon; C ox = ox /t ox is the gate oxide capacitance with ox =3.5x10-11 F/m)
9 The Body Effect V BS (V) V SB is the substrate bias voltage (normally positive for n-channel devices with the body tied to ground) A negative bias V bs causes V T to increase from 0.45V to 0.85V CMPEN 411 L03 S.9
10 Transistor in Linear Mode Assuming V GS > V T S V GS G D V DS I D n+ - V(x) + n+ x B The current is a linear function of both V GS and V DS CMPEN 411 L03 S.10
11 Voltage-Current Relation: Linear Mode For long-channel devices (L > 0.25 micron) When V DS V GS V T where I D = k n W/L [(V GS V T )V DS V DS2 /2] k n = n C ox = n ox /t ox = is the process transconductance parameter ( n is the carrier mobility (m 2 /Vsec)) k n = k n W/L is the gain factor of the device For small V DS, there is a linear dependence between V DS and I D, hence the name resistive or linear region CMPEN 411 L03 S.11
12 Transistor in Saturation Mode Assuming V GS > V T S V GS G D V DS I D V DS > V GS - V T n+ - V GS - V + n+ T B Pinch-off The current remains constant (transistor saturates) CMPEN 411 L03 S.12
13 Voltage-Current Relation: Saturation Mode For long channel devices When V DS V GS V T I D = k n /2 W/L [(V GS V T ) 2 ] since the voltage difference over the induced channel (from the pinch-off point to the source) remains fixed at V GS V T However, the effective length of the conductive channel is modulated by the applied V DS, so I D = I D (1 + V DS ) where is the channel-length modulation (varies with the inverse of the channel length) CMPEN 411 L03 S.13
14 Current Determinates For a fixed V DS and V GS (> V T ), I DS is a function of the distance between the source and drain L the channel width W the threshold voltage V T the thickness of the SiO 2 t ox the dielectric of the gate insulator (e.g., SiO 2 ) ox the carrier mobility - for nfets: n = 500 cm 2 /V-sec - for pfets: p = 180 cm 2 /V-sec CMPEN 411 L03 S.14
15 Long Channel I-V Plot (NMOS) X 10-4 V DS = V GS - V T Linear 1.57V V GS = 2.5V 2.07V V GS = 2.0V Saturation V GS = 1.5V cut-off V 1.07V V GS = 1.0V V DS (V) NMOS transistor, 0.25um, L d = 10um, W/L = 1.5, V DD = 2.5V, V T = 0.43V CMPEN 411 L03 S.16
16 Short Channel Effects Behavior of short channel device mainly due to 10 5 Velocity saturation the velocity of the carriers saturates due to scattering (collisions suffered by the carriers) 0 c = (V/ m) For an NMOS device with L of.25 m, only a couple of volts difference between D and S are needed to reach velocity saturation CMPEN 411 L03 S.17
17 Voltage-Current Relation: Velocity Saturation For short channel devices Linear: When V DS V GS V T where I D = (V DS ) k n W/L [(V GS V T )V DS V DS2 /2] (V) = 1/(1 + (V/ c L)) is a measure of the degree of velocity saturation Saturation: When V DS = V DSAT V GS V T I DSat = (V DSAT ) k n W/L [(V GS V T )V DSAT V DSAT2 /2] CMPEN 411 L03 S.18
18 Velocity Saturation Effects 10 For short channel devices and large enough V GS V T 0 V DSAT < V GS V T so the device enters saturation before V DS reaches V GS V T and operates more often in saturation I DSAT has a linear dependence wrt V GS so a reduced amount of current is delivered for a given control voltage CMPEN 411 L03 S.19
19 Short Channel I-V Plot (NMOS) X 10-4 Early Velocity Saturation V GS = 2.5V V GS = 2.0V 1 Linear Saturation V GS = 1.5V 0.5 V GS = 1.0V V DS (V) NMOS transistor, 0.25um, L d = 0.25um, W/L = 1.5, V DD = 2.5V, V T = 0.43V CMPEN 411 L03 S.20
20 Long Channel I-V Plot (NMOS) X 10-4 V DS = V GS - V T Linear 1.57V V GS = 2.5V 2.07V V GS = 2.0V Saturation V GS = 1.5V cut-off V 1.07V V GS = 1.0V V DS (V) NMOS transistor, 0.25um, L d = 10um, W/L = 1.5, V DD = 2.5V, V T = 0.43V CMPEN 411 L03 S.21
21 MOS I D -V GS Characteristics X V GS (V) Linear (short-channel) versus quadratic (longchannel) dependence of I D on V GS in saturation Velocity-saturation causes the shortchannel device to saturate at substantially smaller values of V DS resulting in a substantial drop in current drive (for V DS = 2.5V, W/L = 1.5) CMPEN 411 L03 S.22
22 Short Channel I-V Plot (PMOS) All polarities of all voltages and currents are reversed -2 V DS (V) V GS = -1.0V -0.2 V GS = -1.5V -0.4 V GS = -2.0V V GS = -2.5V -1 X 10-4 PMOS transistor, 0.25um, L d = 0.25um, W/L = 1.5, V DD = 2.5V, V T = -0.4V CMPEN 411 L03 S.23
23 The MOS Current-Source Model G I D = 0 for V GS V T 0 S I D D I D = k W/L [(V GS V T )V min V min2 /2](1+ V DS ) for V GS V T 0 B with V min = min(v GS V T, V DS, V DSAT ) and V GT = V GS - V T Determined by the voltages at the four terminals and a set of five device parameters V T0 (V) (V 0.5 ) V DSAT (V) k (A/V 2 ) (V -1 ) NMOS x PMOS x CMPEN 411 L03 S.24
24 Other (Submicon) MOS Transistor Concerns Velocity saturation Subthreshold conduction (aka weak inversion) Transistor is already partially conducting for voltages below V T Threshold variations In long-channel devices, the threshold is a function of the length (for low V DS ) In short-channel devices, there is a drain-induced threshold barrier lowering (DIBL) at the upper end of the V DS range (for small L) Parasitic resistances G resistances associated with the source and drain contacts S R S R D D Latch-up CMPEN 411 L03 S.25
25 Subthreshold Conductance Subthreshold exponential region V T Quadratic region Linear region Transition from ON to OFF is gradual (decays exponentially) Current roll-off (slope factor) is also affected by increase in temperature S = n (kt/q) ln (10) (typical values 60 to 100 mv/decade) V GS (V) I D ~ I S e (qv GS /nkt) where n 1 Has repercussions in dynamic circuits and for power consumption CMPEN 411 L03 S.26
26 Subthreshold I D vs V GS I D = I S e (qv GS /nkt) (1 - e (qv DS /kt) )(1 + V DS ) V GS from 0 to 0.5V CMPEN 411 L03 S.27
27 Subthreshold I D vs V DS I D = I S e (qv GS /nkt) (1 - e (qv DS /kt) )(1 + V DS ) V DS from 0 to 0.3V CMPEN 411 L03 S.28
28 Threshold Variations V T V T Long channel threshold Low V DS threshold Threshold varies as a function of the length of the transistor (for low V DS ) L V DS For short channel devices, the threshold varies as a function of V DS - drain-induced barrier lowering (DIBL) CMPEN 411 L03 S.29
29 DIBL increasing V DS V GS (V) For high V DS, the drain depletion region interacts with the source near the channel surface lowering the source potential barrier. The source then injects carriers into the channel without the gate playing a role. DIBL is enhanced at higher V DS and shorter L. CMPEN 411 L03 S.30
30 Next Time: The CMOS Inverter Next lecture CMOS inverter a static view - Reading assignment Rabaey, et al, V DD V in V out C L CMPEN 411 L03 S.31
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