Integrated Circuits & Systems


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1 Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 16 CMOS Combinational Circuits  2
2 Switch Delay Models for Complementary Gates NAND2 INV NOR2 A R p B R p A R p B R p A R n C L R n A C L A R p C int B R n C int R n A R n B C L Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 16.2
3 Complementary Logic Dynamic Behavior 4input NAND R 5 R 6 R 7 A B C D R 8 A B C D R 4 A C L A B C 3 C L R 3 B C 3 C C 2 R 2 C 2 D C 1 C R 1 D C 1 Slide 16.3
4 Complementary Logic Dynamic Behavior 4input NAND Intracell capacitances cannot be disregarded Distributed RC model ( Elmore Delay ) t phl = 0,69 (R 1 C 1 + (R 1 +R 2 ) C (R 1 +R 2 +R 3 ) C 3 + (R 1 +R 2 +R 3 +R 4 ) C L ) A R 5 B R 4 A R 3 B R 6 C R 7 C 3 D R 8 C L If R 1 =R 2 =R 3 =R 4 =R N then: t phl = 0.69 R N x (C 1 +2C 2 +3C 3 +4C L ) Intracell capacitances consist of: junction source and drain capacitances and gatetosource and gatetodrain capacitances. R 2 C R 1 D C 2 C 1 Slide 16.4
5 Problems with Static CMOS Style 1. Ninput gates require 2N transistors 2. Propagation delay deteriorates rapidly as a function of the fanin (i.e., number of inputs) Intrinsic capacitance increases linearly with the number of inputs. The series connection of transistors causes an additional slowdown Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 16.5
6 Propagation Delay as a Function of FanIn Propagation delay of CMOS NAND gate approx. quadratic t p (ps) t phl t p t p t plh LH linear fanin Gates with more than 4 inputs should be avoided Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 16.6
7 Propagation Delay as a Function of FanOut t p (psec) t p NOR2 t p NAND2 t p INV All gates have the same drive current. Slope is a function of driving strength eff. fanout Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 16.7
8 Propagation Delay as a Function of FanOut Fanin: quadratic due to increasing resistance and capacitance Fanout: each additional fanout gate adds two gate capacitances to C L t p = a 1 FI + a 2 FI 2 + a 3 FO Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 16.8
9 Spice Simulations for 4input NAND Modify file nand2v0.cir ( CMOS/ ) A B C D A C L B C D C 3 C 2 C 1 Slide 16.9
10 Spice Simulations for 4input NAND Results t plh t phl A=B=C=B= B=C=D=1 A= A=C=D=1 B= A=B=D=1 C= A=B=C=1 D= Slide 16.10
11 Design Techniques for Static CMOS Gates Transistor Sizing 15,4µm 4,8µm 4,8µm Only effective when the load is dominated by the fanout (not by the intrinsec capacitance) x x x x 4,8µm 4,8µm Gnd Slide 16.11
12 Design Techniques for Static CMOS Gates Progressive Sizing In N MN C L t phl = 0,69 (R 1 C 1 + (R 1 +R 2 ) C (R 1 +R 2 +R 3 ) C 3 + (R 1 +R 2 +R 3 +R 4 ) C L ) In 3 In 2 M3 M2 C 3 C 2 Equalize efective resistances by: W M1 > W M2 > W M3 > > W MN In 1 M1 C 1 Up to 20% gate delay reduction can be achieved (according to Rabaey) Problem: difficult to be accomplished in layout, due to different Ws. Slide 16.12
13 Design Techniques for Static CMOS Gates Transistor Reordering Critical path Critical path In 3 1 In 2 1 In M3 M2 M1 C 2 C 1 C L charged charged charged 0 1 In 1 M3 In 2 1 M2 In 3 1 M1 C 2 C 1 C L charged charged charged Delay determined by the time to discharge C L, C 1 e C 2 Delay determined by the time to discharge C L Slide Source: Rabaey; Chandrakasan; Nikolic, 2003
14 Design Techniques for Static CMOS Gates Logic Decomposition/Restructuring F = ABCDEFGH High fanin (avoid) Twolevel CMOS logic Fanin of 2, unitary fanout Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 16.14
15 Design Techniques for Static CMOS Gates Bufer Insertion Isolate anin from fanout C L C L C L may represent the capacitance o a long wire (e.g., a bus line) Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 16.15
16 Ratioed Logic Resistive load R L S Depletion transist. V T <0 S PMOS transist S PDN PDN PDN Resistive Load (general idea) with depletion transistor PseudoNMOS Target: transistor reduction Problem: the nominal low output voltage (V OL ) is not 0 V. Slide 16.16
17 Ratioed Logic Resistive load PDN R L S N+1 transistors V OH = V OL = R PN /(R PN + R L ) Asymmetric response Static power consumption Tp L = 0,69 R L C L Slide 16.17
18 Ratioed Logic Active Load Depletion transist. V T <0 PMOS transist S S PDN PDN with depletion transistor PseudoNMOS Smaller Area & self load But static power dissipation and V OL > 0 (less robust to noise) Slide 16.18
19 Ratioed Logic Features (Noise Margins) To improve robustness V OL must be as small => k p << k n (=> W p << W n ) With W p << W n => tp LH increases Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 16.19
20 Ratioed Logic Features (VTC) Effect of sizing the PMOS transistor in a pseudonmos inverter 3.0 Ratios W/L p < 1 => L p > W p (> L min ) 2.5 size V OL Static power tp LH 2.0 W/L p = V 564µW 14ps V 298µW 56ps V o u t [V] W/L p = V 160µW 123ps V 80µW 268ps V 41µW 569ps 0.5 W/L p = 0.5 W/L p = W/L p = 1 Slide V in [V] Source: Rabaey; Chandrakasan; Nikolic, 2003
21 Application of Ratioed Logic to PLAs But, applying De Morgan s theorem A B AND Plane OR Plane C D imput buffers m n outputs A B inputs Slide C D
22 Application of Ratioed Logic to PLAs PseudoNMOS to realize a manyinput NOR gate NOR Plane 1 NOR Plane 2 S n A B C D imput buffers m outputs inputs Slide 16.22
23 Improved Ratioed Logic Differential Cascode Voltage Switch Logic (DCVSL) When PDN1 conducts, PDN2 is off (and vice versa) Each input must be provided in complementary format out M 1 M 2 PDN1 PDN2 The feedback mechanism turns off the load device that is not used out Slide 16.23
24 Improved Ratioed Logic  DCVSL Circuit is in steady state (no current flows) out on off M 1 M out PDN1 PDN2 no path to Gnd there is a path to Gnd Slide 16.24
25 Improved Ratioed Logic  DCVSL PDN1 must bring out below V DD  V Tp on off A new input vector is applied out M 1 M 2 PDN1 PDN2 0 out Becomes in high impedance (M2 and PDN2 are both off) there is a path to Gnd no path to Gnd Slide 16.25
26 Improved Ratioed Logic  DCVSL ( < V DD  V Tp ) out on turns on M 1 M 2 out A new input vector is applied PDN1 PDN2 there is a path to Gnd no path to Gnd Slide 16.26
27 Improved Ratioed Logic  DCVSL turns turns on M 1 off M 2 ( < V DD  V Tp ) ( > V DD  V Tp ) out out A new input vector is applied PDN1 PDN2 there is a path to Gnd no path to Gnd Slide 16.27
28 Improved Ratioed Logic  DCVSL out is completely discharged through this path (when no more current flows) out off on M 1 M 2 out out is completely charged through this path (when no more current flows) A new input vector is applied PDN1 PDN2 there is a path to Gnd no path to Gnd Slide 16.28
29 Improved Ratioed Logic  DCVSL Circuit reaches steady state No current out off on M 1 M out No current A new input vector is applied PDN1 PDN2 there is a path to Gnd no path to Gnd Slide 16.29
30 Improved Ratioed Logic  DCVSL M 1 M 2 out out PDN1 PDN2 Full railtorail swing No static currents However: During transition, short circuit current (dynamic consumption) Device rationing is still important for functionality (not only for performance) Slide 16.30
31 V o l t a g e [V] CMOS Combinational Circuits Improved Ratioed Logic  DCVSL AND/NAND Gate Transient Response A,B A, B out=a.b out =A.B 1.5µm/ 0.25µm out M 1 M 2 M 3 M 4 1.0µm/ 0.25µm M 5 M 6 1.5µm/ 0.25µm 0.5µm/ 0.25µm out Time [ns] Source: Rabaey; Chandrakasan; Nikolic, 2003 tp(out)= 197ps tp(out )= 321ps Slide 16.31
32 Improved Ratioed Logic  DCVSL XORXNOR Gate Source: Rabaey; Chandrakasan; Nikolic, 2003 It is possible to share transistors among the two PDNs, thus reducing the overhead Slide 16.32
33 CMOS Combinational References Circuits 1. RABAEY, J; CHANDRAKASAN, A.; NIKOLIC, B. Digital Integrated Circuits: a design perspective. 2 nd Edition. Prentice Hall, ISBN: WESTE, Neil; HARRIS, David. CMOS VLSI Design: a circuits and systems perspective. AddisonWesley, 4 th Edition, ISBN Slide 16.33
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