ESE 570: Digital Integrated Circuits and VLSI Fundamentals


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1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 8: February 9, 016 MOS Inverter: Static Characteristics
2 Lecture Outline! Voltage Transfer Characteristic (VTC) " Static Discipline Noise Margins! Resistive Load Inverter Analysis! Design Perspective
3 Voltage Transfer Characteristic (VTC)
4 Ideal Voltage Transfer Characteristic (VTC) V in V out Logic 0 = 0 V Logic 1 = 0 4
5 Actual Voltage Transfer Characteristic (VTC) V OH o.c. C out V OL 0 For DC steadystate C out is open circuit. 0 V OL V T0n 5
6 Noise Immunity and Noise Margins V OH max output voltage when the logic output is 1 V OL 0 min output voltage when the logic output is 0 V IL max input voltage that can be interpreted as a logic 0 V IH min input voltage that can be interpreted as a logic 1 NOTE: V IL V OL and V IH V OH 6
7 Noise Immunity and Noise Margins Slope of VTC or inverter gain 7
8 Resistive Load Inverter Analysis
9 Resistive Load Inverter V SB 9
10 Resistive Load Inverter Resistor: I L = V out V SB 10
11 Resistive Load Inverter Resistor: I L = V out Subthreshold: V in = V GS < V T 0,n! W I D = I S " L! " &e % V in V T 0,n nkt /q & %!! " 1 e " V out & kt /q % & % V SB 11
12 Resistive Load Inverter Resistor: I L = V out Subthreshold: V in = V GS < V T 0,n! W I D = I S " L Linear:! " &e % V in V T 0,n nkt /q & %!! " 1 e " V out & kt /q % V in = V GS V T 0,n,V out = V DS V in V T 0,n & % V SB I D = µ n C ox W L ( V in V T 0,n )V out V out ( ) 1
13 Resistive Load Inverter Resistor: I L = V out Subthreshold: V in = V GS < V T 0,n! W I D = I S " L Linear:! " &e % V in V T 0,n nkt /q & %!! " 1 e " V out & kt /q % V in = V GS V T 0,n,V out = V DS V in V T 0,n & % V SB I D = µ n C ox Saturation: W L ( V in V T 0,n )V out V out ( ) V in = V GS V T 0,n,V out = V DS > V in V T 0,n I D = µ n C ox W ( L V in V T 0,n ) 13
14 Resistive Load Inverter Resistor: I L = V out Subthreshold: V in = V GS < V T 0,n! W I D = I S " L Linear:! " &e % V in V T 0,n nkt /q & %!! " 1 e " V out & kt /q % & % I D = 0 V in = V GS V T 0,n,V out = V DS V in V T 0,n V SB I D = µ n C ox Saturation: W L ( V in V T 0,n )V out V out ( ) V in = V GS V T 0,n,V out = V DS > V in V T 0,n I D = µ n C ox W ( L V in V T 0,n ) 14
15 Resistive Load Inverter V SB 15
16 Resistive Load Inverter: V OH V SB Resistor/Load: Transistor: Subthreshold 16
17 Resistive Load Inverter: V OH V SB Resistor/Load: Transistor: Subthreshold I L = V out I D = 0 0 = V out V out = = V OH 17
18 Resistive Load Inverter: V OL V SB Resistor/Load: Transistor: Linear 18
19 Resistive Load Inverter: V OL V SB Resistor/Load: I L = V out Transistor: Linear I D = µ n C ox W L ( V in V T 0,n )V out V out ( ) V in =,V out = V OL V OL = µ C n ox W L ( V T 0,n)V OL V OL ( ) 19
20 Resistive Load Inverter: V OL (con t) Resistor/Load: I L = V out Transistor: Linear I D = µ n C ox W L ( V in V T 0,n )V out V out ( ) V in =,V out = V OL V OL % = µ n C ox W L ( V T 0,n )V OL V OL ( ) W = µ n C ox L V OL = ( ( V T 0,n )V OL V OL ) 1 & (( V OL ) = ( V T 0,n )V OL V OL ' V OL V T 0,n + 1 & % (V OL + = 0 ' 0
21 Resistive Load Inverter: V OL (con t) Resistor/Load: I L = V out Transistor: Linear I D = µ n C ox W L ( V in V T 0,n )V out V out ( ) V in =,V out = V OL = µ n C ox W L V " V V + 1 % OL DD T 0,n 'V OL + = 0 & V OL = " V T 0,n + 1 % " " '± V T 0,n + 1 %% '' & && " V OL = V T 0,n + 1 % " '± V T 0,n + 1 % ' & & 4 1
22 Resistive Load Inverter: V OL (con t) Resistor/Load: I L = V out Transistor: Linear I D = µ n C ox W L ( V in V T 0,n )V out V out ( ) V in =,V out = V OL = µ n C ox W L V " V V + 1 % OL DD T 0,n 'V OL + = 0 & V OL = " V T 0,n + 1 % " " '± V T 0,n + 1 %% '' & && " V OL = V T 0,n + 1 % " '± V T 0,n + 1 % ' & & 4 0 < V OL < V T 0,n
23 Resistive Load Inverter: V IL V SB Resistor/Load: Transistor: Saturation 3
24 Resistive Load Inverter: V IL V SB Resistor/Load: I L = V out Transistor: Saturation I D = µ n C ox W ( L V in V T 0,n ) V out = µ C n ox W ( L V V in T 0,n) 4
25 Resistive Load Inverter: V IL (con t) V out = µ n C ox W ( L V V in T 0,n) Differentiate W.R.T. V in : 1 dv out dv in W = µ n C ox ( L V in V T 0,n ) 1 W = µ n C ox ( L V IL V T 0,n ) V out Vin =V IL V out Vin =V IL V IL = 1 +V T 0,n V V in =V IL : = V out Vin =V IL = ( V V IL T 0,n) ( V IL V T 0,n ) 1 = 5
26 Resistive Load Inverter: V IH V SB Resistor/Load: Transistor: Linear 6
27 Resistive Load Inverter: V IH V SB Resistor/Load: I L = V out I D = µ n C ox Transistor: Linear W L ( V in V T 0,n )V out V out ( ) V out = µ n C ox W L ( V V in T 0,n)V out V out ( ) 7
28 Resistive Load Inverter: V IH V out = µ n C ox W L ( V V in T 0,n)V out V out ( ) Differentiate W.R.T. V in : 1 dv out dv in = k " n V V in T 0,n ( ) dv out dv in 1 = V IH V T 0,n + V out V out dv out dv in ( ( ) + 4V out ) 1 = V T 0,n V IH + V out V IH = V T 0,n + V out 1 % ' & 8
29 Resistive Load Inverter: V IH V out = µ n C ox W L ( V V in T 0,n)V out V out ( ) V IH = V T 0,n + V out 1 Substitute: V out = k " n " V + V 1 % % T 0,n out V T 0,n 'V out V out R ' L & & V out = k " n 4V % out V out V out ' & = k " n 3V % out V out '+ V out & = 3 V out V out + V out = 3 V out V out Vin =V IH = 3 V IH = V T 0,n
30 Inverter Threshold: V th V out V th = µ n C ox W ( L V V in T 0,n) = ( V V th T 0,n) V th = V th V th V T 0,n +V T 0,n 0 = V V 1 & th % T 0,n (V th +V T 0,n ' V T 0,n + 1 & % (± V T 0,n 1 && % % (( ' '' V th = V th = V T 0,n + 1 ± V T 0,n 1 & % ( ' 4 V V & DD % T 0,n ( ' V V & DD % T 0,n ( ' 30
31 Summary: Resistive Load Inverter 0 V T0n 31
32 Summary: Resistive Load Inverter Take Limit as > > V T0n > V T0n > > V T0n > 0 > 0 V out > VDD > semiideal VTC 0 0 VV T0n T0n V in 3
33 Example V OL = V or V? 33
34 Example (con t) Preferred Design
35 Design Perspective
36 Noise Implications! What is the output when all inputs are all 1s? 36
37 Noise Implications! What is the output when all inputs are all 1.0 and NAND(A, B) = 1A*B? 37
38 Noise Implications! What is the output when all inputs are all 0.95 and NAND(A, B) = 1A*B? 38
39 Degradation! Cannot have signal degrade across cascaded gates! Want to be able to cascade arbitrary set of gates " No limit on number of gates to maintain signal integrity 39
40 Gate Creed! Gates should leave the signal better than they found it " better closer to the rails 40
41 Regeneration Discipline! Define legal inputs " Gate works if V in close enough to the rail! Regeneration " Gate produces V out closer to rail " This tolerates some drop between one gate and next (between out and in) " Call this our Noise Margin Regeneration/Restoration/Static Discipline 41
42 Noise Margin! V OH output high! V OL output low 1 V OH! V IH input high! V IL input low NM H V IH Undefined region V IL NM L V OL! NM H = V OH V IH! NM L = V IL V OL 0 Gate Output Stage M Gate Input Stage M + 1 4
43 Regeneration Discipline (getting precise)! Define legal inputs " Gate works if V in close enough to the rail 1 " V in > V IH or V in < V IL V OH NM H V IH! Regeneration Undefined region " Gate produces V out closer to rail V OL NM L V IL " V out < V OL or V out > V OH 0 Gate Output Stage M Gate Input Stage M
44 Decomposing! An input closer to rail than V IL, V IH doesn t make much difference on V out " i.e transfer function is flat close to rails V OH V IH 1 NM H! Defining V IL lower (V IH higher) would reduce NMs and increase our undefined region V IL V OL V IL 1 V IH δv out δv in V IL = δv out δv in V IH = 1 NM L V OH = f (V IL ) V OL = f (V IH ) 44
45 Big Idea! Need robust logic " Can design into any (feed forward) graph with logic gates and tolerate loss and noise, while maintaining digital abstraction! Regeneration and noise margins " Every gate makes signal better " Design level of noise tolerance V OH 1 NM H V IH V IL V OL 1 NM L V IL V IH 45
46 Admin! HW handback! HW 4 due Thursday, /18 " If you submit online and inclass only the online one will be graded.! Journal Thursday " Gregory Fredeman, et. al., A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access, pp
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