# 6.012 MICROELECTRONIC DEVICES AND CIRCUITS

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1 MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Science MICROELECTRONIC DEVICES AND CIRCUITS Answers to Exam 2 Spring 2008 Problem 1: Graded by Prof. Fonstad a) i) nchannel MOSFET: Enhancement mode because V T 0, which for an n channel MOSFET means that with v GS = 0 there is no channel. ii) pchannel MOSFET: Depletion mode because V T 0, which for a pchannel MOSFET means that with v GS = 0 there is already a channel. Negative because there is a hole inversion layer in the pchannel device, i.e. electrons depleted from the area near the interface and holes attracted to the interface, even with v GS = 0. Concurrently, it takes more gate voltage to invert the channel of the nchannel device, meaning more positive charge must be put on the gate electrode which is balances by negative ions at the interface. iii) Larger, because the charging current is the current in saturation through the p channel device, and since the current in saturation for both of the devices is proportional to (V DD V T ) 2, this current is larger for the pchannel device since for it V T is smaller. iv) Larger, because for both devices V T = V FB 2φ Si (t ox /ε ox )(.) 1/2. making t ox thicker, makes V T larger. b) i) V GS : 2V V BS : 1V V DS : 2V v gs : v AC v ds : v AC v bs : v AC The LEC is a single resistor: r ac = 1/g ac = 1/[g m g mb g o ]= 1/[g m (1η)g o ] Thus ii) iii) iv) LEC: g m g o g mb nchannel, because for a transistor in strong inversion and biased in saturation, g m = (2KI D ) 1/2 and we can assume that K n > K p because in general µ e > µ h. Similar, because for a transistor operating subthreshold g m = qi D /nkt, and the I D s are equal and the n s will be similar. In the linear region i D = K(v GS V T v DS /2)v DS g ac Transconductance: g m = i D / v GS Q = KV DS Output conductance: g o = i D / v DS Q = [K(v GS V T v DS /2)Kv DS /2] Q =K(V GS V T V DS )

2 Problem 2: Graded by Prof. Palacios a) The i D v DS plot shows us that for the gate voltage applied the MOSFET saturates at a v DS of V. We can find out what the gate voltage is using: V DS,sat = V GS V T : V GS = V DS,sat V T = V 1 V = 6 V b) Near the origin, i D = K(v GS V T v DS /2)v DS and the slope is K(v GS V T v DS ). Evaluating this at the origin, we find that i D / v DS V DS = 0) = K(V GS V T ) = KV DS,sat where (V GS V T ) = V. To find K and evaluate this we can use the saturation current, 10 ma, and saturation voltage, V, in i D,sat = K(v GS V T ) 2 /2 =K(V DS,sat ) 2 /2 to find: K = 2i D,sat /(V DS,sat ) 2 = 2 (0.01/2) = A/V 2 With this the slope, KV DS,sat, is: 8 x 10 4 x = 4 x 10 3 S c) At any point in the channel, q N *(y) = (ε ox /t ox )(V GC V T ) = (ε ox /t ox )(V GS V CS V T ) i) At the source end of the channel, V CS = 0, and we find: q N *(0) = (ε ox /t ox )(V GS V T ) = (3. x /10 6 ) = 1.7 x 10 6 C/cm 2 ii) At the drain end of the channel, V CS = V DS = 2. V, and we find: q N *(L) = (ε ox /t ox )(V GS V DS V T ) = (3. x /10 6 ) 2. = 8.7 x 10 7 C/cm 2 d) The drift velocity can be found by remembering that i D is the channel current and that the current at any point y along the channel is the sheet charge density in the channel, q N *(y), times the drift velocity of the carriers composing this charge, times the width of the channel: i D = W q N *(y) s edrift (y). Thus: s edrift (y) = i D /W q N *(y) i) At the source end of the channel we find: s edrift (0) = i D /W q N *(y) = 7. x 10 3 / x 10 3 x 1.7 x 10 6 = 8.7 x 1 cm/s ii) At the drain end of the channel we find: s edrift (L) = i D /W q N *(y) = 7. x 10 3 / x 10 3 x 8.7 x 10 7 = 1.71 x 10 6 cm/s e) Now the relationship between the drain current and the charge density at y = L must be i D = W q N *(L) s sat (y). We want the charge density, so we solve for that: q N *(L) = i D /W s sat (y) = 10 2 / x 10 3 x 10 7 = 2 x 10 7 C/cm 2 f) This is a difficult question and almost nobody got it correct. This was anticipated before the exam, but we decided to leave the question in with a precautionary note added, just to see if anyone could do it. That said, the idea is to go back to the expression for i D along the channel, and to integrate it from y = 0 to y = L/2, the point along the channel at which we want to know v CS. Since we know i D already, we can find v CS (L/2). The sequence leading to the expression sought is: i D,sat = W q N *(y) µ e dv CS /dy = W (ε ox /t ox )[V GS v CS (y)v T ] µ e dv CS /dy i D,sat dy = W (ε ox /t ox )[V GS v CS (y)v T ] µ e dv CS 0 y i D,sat dy = i D,sat y = 0 Vcs(y) W (ε ox /t ox )[V GS v CS V T ] µ e dv CS

3 Problem 3: Graded by Prof. Palacios a) i) ii) b) v IN = V T Cutoff Saturation v OUT = v IN V Tn Linear v OUT = V GG V Tp n: Cutoff p: Linear n: Saturated p: Saturated n: Saturated p: Linear Linear Saturation n: LInear p: Saturated c) The threshold point occurs where both transistors are in saturation. The equation for the curve there is: I Dsat n = (K n /2)(V GSn V Tn ) 2 = I Dsat p = (K p /2)(V SGp V Tp ) 2 We know K n = K p, V Tn = V Tp, V SGp = V DD V GG, and V GSn = V IN = V DD /2, so we find V DD /2 V Tn = V DD V GG V Tp V GG = V DD /2 = 2. V d) When both devices are in saturation at this bias point, the LEC is: v in g m,n v in g o,n v out go,p We find A v = g mn /(g on g op ). There are several ways to write g m in terms of the bias current and voltages, but the most useful here is g mn = 2I Dn /(V GSn V Tn ). This along with g on = λ n I Dn and g op = λ p I Dp, and using I Dn = I Dp = I D, λ n = λ p = 0.1 V 1, V Tn = 1 V, and V GSn = 2. V, lead us to: A v = g mn /(g on g op ) = 2/[(V GSn V Tn )(λ n λ p )] = 2/(1. x 0.2) = 6.6 e) When V IN = V the nchannel device is on, and the pchannel device is saturated with I D = K p (V DD V GG V Tp ) 2 /2. The corresponding static power dissipation is I D V DD. Working through this we find P Static (V IN = V) = I D V DD = [(W P /L P )µ h C * ox (V DD V GG V Tp ) 2 /2] x V DD = (2 x 200 x 6 x 10 7 x 1. 2 ) x /2 = 16.8 x 10 3 W = 16.8 mw You did not have to include channel length modulation in this subsection, but if you did you had an additional term [1 λ(v DS V DS,sat )] = 1 0.1( 1.) = 1.3 multiplying the current, and found: P Static (V IN = V) = 16.8 x 1.3 = 22.7 mw f) When V IN = V the nchannel device is off, and the only static power dissipation is due to the subthreshold current, I D,st, and is I D,st V DD. This is probably negligible, but just to be sure, we start by calculating the subthreshold current when v GS = 0:

4 i D,st = [(W N /L N )µ e C * ox ] (kt/q) 2 (n 1) exp(qv T /nkt) = (10 x x 10 2 x 6 x 10 7 ) (2. x 10 2 ) 2 (1. 1) exp[1/(1. x 0.02)] 9.3 x 10 7 e 27 A 9.3 x 10 7 x 1.6 x x From this we have P Static (V IN = 0V) = 1. x x W 0. g) The low to high transition time is due to charging through the pchannel device with its saturation current, I D = K p (V DD V GG V Tp ) 2 /2 [= 3.36 ma from Part (e)], so we have: τ LoHi = C L V DD /[K p (V DD V GG V Tp ) 2 /2] = x /(3.36 x 10 3 ) = 1.48 x s Exam Statistics Average/Standard deviation: Problem 1 Problem Problem Total Class median: 73 Distribution to nearest : Find your face in this picture Total Score σ Ave Median σ

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