6.012 MICROELECTRONIC DEVICES AND CIRCUITS

Size: px
Start display at page:

Download "6.012 MICROELECTRONIC DEVICES AND CIRCUITS"

Transcription

1 MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Science MICROELECTRONIC DEVICES AND CIRCUITS Answers to Exam 2 Spring 2008 Problem 1: Graded by Prof. Fonstad a) i) nchannel MOSFET: Enhancement mode because V T 0, which for an n channel MOSFET means that with v GS = 0 there is no channel. ii) pchannel MOSFET: Depletion mode because V T 0, which for a pchannel MOSFET means that with v GS = 0 there is already a channel. Negative because there is a hole inversion layer in the pchannel device, i.e. electrons depleted from the area near the interface and holes attracted to the interface, even with v GS = 0. Concurrently, it takes more gate voltage to invert the channel of the nchannel device, meaning more positive charge must be put on the gate electrode which is balances by negative ions at the interface. iii) Larger, because the charging current is the current in saturation through the p channel device, and since the current in saturation for both of the devices is proportional to (V DD V T ) 2, this current is larger for the pchannel device since for it V T is smaller. iv) Larger, because for both devices V T = V FB 2φ Si (t ox /ε ox )(.) 1/2. making t ox thicker, makes V T larger. b) i) V GS : 2V V BS : 1V V DS : 2V v gs : v AC v ds : v AC v bs : v AC The LEC is a single resistor: r ac = 1/g ac = 1/[g m g mb g o ]= 1/[g m (1η)g o ] Thus ii) iii) iv) LEC: g m g o g mb nchannel, because for a transistor in strong inversion and biased in saturation, g m = (2KI D ) 1/2 and we can assume that K n > K p because in general µ e > µ h. Similar, because for a transistor operating subthreshold g m = qi D /nkt, and the I D s are equal and the n s will be similar. In the linear region i D = K(v GS V T v DS /2)v DS g ac Transconductance: g m = i D / v GS Q = KV DS Output conductance: g o = i D / v DS Q = [K(v GS V T v DS /2)Kv DS /2] Q =K(V GS V T V DS )

2 Problem 2: Graded by Prof. Palacios a) The i D v DS plot shows us that for the gate voltage applied the MOSFET saturates at a v DS of V. We can find out what the gate voltage is using: V DS,sat = V GS V T : V GS = V DS,sat V T = V 1 V = 6 V b) Near the origin, i D = K(v GS V T v DS /2)v DS and the slope is K(v GS V T v DS ). Evaluating this at the origin, we find that i D / v DS V DS = 0) = K(V GS V T ) = KV DS,sat where (V GS V T ) = V. To find K and evaluate this we can use the saturation current, 10 ma, and saturation voltage, V, in i D,sat = K(v GS V T ) 2 /2 =K(V DS,sat ) 2 /2 to find: K = 2i D,sat /(V DS,sat ) 2 = 2 (0.01/2) = A/V 2 With this the slope, KV DS,sat, is: 8 x 10 4 x = 4 x 10 3 S c) At any point in the channel, q N *(y) = (ε ox /t ox )(V GC V T ) = (ε ox /t ox )(V GS V CS V T ) i) At the source end of the channel, V CS = 0, and we find: q N *(0) = (ε ox /t ox )(V GS V T ) = (3. x /10 6 ) = 1.7 x 10 6 C/cm 2 ii) At the drain end of the channel, V CS = V DS = 2. V, and we find: q N *(L) = (ε ox /t ox )(V GS V DS V T ) = (3. x /10 6 ) 2. = 8.7 x 10 7 C/cm 2 d) The drift velocity can be found by remembering that i D is the channel current and that the current at any point y along the channel is the sheet charge density in the channel, q N *(y), times the drift velocity of the carriers composing this charge, times the width of the channel: i D = W q N *(y) s edrift (y). Thus: s edrift (y) = i D /W q N *(y) i) At the source end of the channel we find: s edrift (0) = i D /W q N *(y) = 7. x 10 3 / x 10 3 x 1.7 x 10 6 = 8.7 x 1 cm/s ii) At the drain end of the channel we find: s edrift (L) = i D /W q N *(y) = 7. x 10 3 / x 10 3 x 8.7 x 10 7 = 1.71 x 10 6 cm/s e) Now the relationship between the drain current and the charge density at y = L must be i D = W q N *(L) s sat (y). We want the charge density, so we solve for that: q N *(L) = i D /W s sat (y) = 10 2 / x 10 3 x 10 7 = 2 x 10 7 C/cm 2 f) This is a difficult question and almost nobody got it correct. This was anticipated before the exam, but we decided to leave the question in with a precautionary note added, just to see if anyone could do it. That said, the idea is to go back to the expression for i D along the channel, and to integrate it from y = 0 to y = L/2, the point along the channel at which we want to know v CS. Since we know i D already, we can find v CS (L/2). The sequence leading to the expression sought is: i D,sat = W q N *(y) µ e dv CS /dy = W (ε ox /t ox )[V GS v CS (y)v T ] µ e dv CS /dy i D,sat dy = W (ε ox /t ox )[V GS v CS (y)v T ] µ e dv CS 0 y i D,sat dy = i D,sat y = 0 Vcs(y) W (ε ox /t ox )[V GS v CS V T ] µ e dv CS

3 Problem 3: Graded by Prof. Palacios a) i) ii) b) v IN = V T Cutoff Saturation v OUT = v IN V Tn Linear v OUT = V GG V Tp n: Cutoff p: Linear n: Saturated p: Saturated n: Saturated p: Linear Linear Saturation n: LInear p: Saturated c) The threshold point occurs where both transistors are in saturation. The equation for the curve there is: I Dsat n = (K n /2)(V GSn V Tn ) 2 = I Dsat p = (K p /2)(V SGp V Tp ) 2 We know K n = K p, V Tn = V Tp, V SGp = V DD V GG, and V GSn = V IN = V DD /2, so we find V DD /2 V Tn = V DD V GG V Tp V GG = V DD /2 = 2. V d) When both devices are in saturation at this bias point, the LEC is: v in g m,n v in g o,n v out go,p We find A v = g mn /(g on g op ). There are several ways to write g m in terms of the bias current and voltages, but the most useful here is g mn = 2I Dn /(V GSn V Tn ). This along with g on = λ n I Dn and g op = λ p I Dp, and using I Dn = I Dp = I D, λ n = λ p = 0.1 V 1, V Tn = 1 V, and V GSn = 2. V, lead us to: A v = g mn /(g on g op ) = 2/[(V GSn V Tn )(λ n λ p )] = 2/(1. x 0.2) = 6.6 e) When V IN = V the nchannel device is on, and the pchannel device is saturated with I D = K p (V DD V GG V Tp ) 2 /2. The corresponding static power dissipation is I D V DD. Working through this we find P Static (V IN = V) = I D V DD = [(W P /L P )µ h C * ox (V DD V GG V Tp ) 2 /2] x V DD = (2 x 200 x 6 x 10 7 x 1. 2 ) x /2 = 16.8 x 10 3 W = 16.8 mw You did not have to include channel length modulation in this subsection, but if you did you had an additional term [1 λ(v DS V DS,sat )] = 1 0.1( 1.) = 1.3 multiplying the current, and found: P Static (V IN = V) = 16.8 x 1.3 = 22.7 mw f) When V IN = V the nchannel device is off, and the only static power dissipation is due to the subthreshold current, I D,st, and is I D,st V DD. This is probably negligible, but just to be sure, we start by calculating the subthreshold current when v GS = 0:

4 i D,st = [(W N /L N )µ e C * ox ] (kt/q) 2 (n 1) exp(qv T /nkt) = (10 x x 10 2 x 6 x 10 7 ) (2. x 10 2 ) 2 (1. 1) exp[1/(1. x 0.02)] 9.3 x 10 7 e 27 A 9.3 x 10 7 x 1.6 x x From this we have P Static (V IN = 0V) = 1. x x W 0. g) The low to high transition time is due to charging through the pchannel device with its saturation current, I D = K p (V DD V GG V Tp ) 2 /2 [= 3.36 ma from Part (e)], so we have: τ LoHi = C L V DD /[K p (V DD V GG V Tp ) 2 /2] = x /(3.36 x 10 3 ) = 1.48 x s Exam Statistics Average/Standard deviation: Problem 1 Problem Problem Total Class median: 73 Distribution to nearest : Find your face in this picture Total Score σ Ave Median σ

5 MIT OpenCourseWare Microelectronic Devices and Circuits Fall 2009 For information about citing these materials or our Terms of Use, visit:

Lecture 28 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 18, 2007

Lecture 28 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 18, 2007 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 28-1 Lecture 28 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 18, 2007 Contents: 1. Second-order and

More information

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

More information

Microelectronic Devices and Circuits Lecture 13 - Linear Equivalent Circuits - Outline Announcements Exam Two -

Microelectronic Devices and Circuits Lecture 13 - Linear Equivalent Circuits - Outline Announcements Exam Two - 6.012 Microelectronic Devices and Circuits Lecture 13 Linear Equivalent Circuits Outline Announcements Exam Two Coming next week, Nov. 5, 7:309:30 p.m. Review Subthreshold operation of MOSFETs Review Large

More information

6.012 Electronic Devices and Circuits Spring 2005

6.012 Electronic Devices and Circuits Spring 2005 6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):

More information

Lecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.)

Lecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.) Lecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.) Outline 1. The saturation region 2. Backgate characteristics Reading Assignment: Howe and Sodini, Chapter 4, Section 4.4 6.012 Spring 2009 Lecture

More information

CMOS scaling rules Power density issues and challenges Approaches to a solution: Dimension scaling alone Scaling voltages as well

CMOS scaling rules Power density issues and challenges Approaches to a solution: Dimension scaling alone Scaling voltages as well 6.01 - Microelectronic Devices and Circuits Lecture 16 - CMOS scaling; The Roadmap - Outline Announcements PS #9 - Will be due next week Friday; no recitation tomorrow. Postings - CMOS scaling (multiple

More information

6.012 Electronic Devices and Circuits

6.012 Electronic Devices and Circuits Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to

More information

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!

More information

Lecture 29 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 20, 2007

Lecture 29 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 20, 2007 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 29-1 Lecture 29 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 20, 2007 Contents: 1. Non-ideal and second-order

More information

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing

More information

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula

More information

MOSFET Physics: The Long Channel Approximation

MOSFET Physics: The Long Channel Approximation MOSFET Physics: The ong Channel Approximation A basic n-channel MOSFET (Figure 1) consists of two heavily-doped n-type regions, the Source and Drain, that comprise the main terminals of the device. The

More information

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOS Capacitor with External Bias

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOS Capacitor with External Bias ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 5: Januar 6, 17 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation! Level

More information

MOS Transistor I-V Characteristics and Parasitics

MOS Transistor I-V Characteristics and Parasitics ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

More information

The Gradual Channel Approximation for the MOSFET:

The Gradual Channel Approximation for the MOSFET: 6.01 - Electronic Devices and Circuits Fall 003 The Gradual Channel Approximation for the MOSFET: We are modeling the terminal characteristics of a MOSFET and thus want i D (v DS, v GS, v BS ), i B (v

More information

Chapter 4 Field-Effect Transistors

Chapter 4 Field-Effect Transistors Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation

More information

High-to-Low Propagation Delay t PHL

High-to-Low Propagation Delay t PHL High-to-Low Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (n-channel) immediately switches from cutoff to saturation; the p-channel pull-up switches from triode to

More information

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B) 1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed

More information

Chapter 13 Small-Signal Modeling and Linear Amplification

Chapter 13 Small-Signal Modeling and Linear Amplification Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors

More information

Microelectronic Devices and Circuits Lecture 9 - MOS Capacitors I - Outline Announcements Problem set 5 -

Microelectronic Devices and Circuits Lecture 9 - MOS Capacitors I - Outline Announcements Problem set 5 - 6.012 - Microelectronic Devices and Circuits Lecture 9 - MOS Capacitors I - Outline Announcements Problem set 5 - Posted on Stellar. Due net Wednesday. Qualitative description - MOS in thermal equilibrium

More information

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Lecture 1 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;

More information

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1

More information

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET: Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)

More information

Lecture 30 The Short Metal Oxide Semiconductor Field Effect Transistor. November 15, 2002

Lecture 30 The Short Metal Oxide Semiconductor Field Effect Transistor. November 15, 2002 6.720J/3.43J Integrated Microelectronic Devices Fall 2002 Lecture 30 1 Lecture 30 The Short Metal Oxide Semiconductor Field Effect Transistor November 15, 2002 Contents: 1. Short channel effects Reading

More information

ECE315 / ECE515 Lecture-2 Date:

ECE315 / ECE515 Lecture-2 Date: Lecture-2 Date: 04.08.2016 NMOS I/V Characteristics Discussion on I/V Characteristics MOSFET Second Order Effect NMOS I-V Characteristics ECE315 / ECE515 Gradual Channel Approximation: Cut-off Linear/Triode

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003

Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003 6.12 - Microelectronic Devices and Circuits - Spring 23 Lecture 14-1 Lecture 14 - Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:

More information

MOS Transistor Theory

MOS Transistor Theory CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

More information

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2

More information

Lecture 04 Review of MOSFET

Lecture 04 Review of MOSFET ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices. Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

Quantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current.

Quantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current. Quantitative MOSFET Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current. V DS _ n source polysilicon gate y = y * 0 x metal interconnect to

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering NAME: GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering ECE 4430 First Exam Closed Book and Notes Fall 2002 September 27, 2002 General Instructions: 1. Write on one side of

More information

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view) CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN

More information

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring

More information

Practice 3: Semiconductors

Practice 3: Semiconductors Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given

More information

ELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model

ELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model ELEC 3908, Physical Electronics, Lecture 23 The MOSFET Square Law Model Lecture Outline As with the diode and bipolar, have looked at basic structure of the MOSFET and now turn to derivation of a current

More information

EE105 - Fall 2006 Microelectronic Devices and Circuits

EE105 - Fall 2006 Microelectronic Devices and Circuits EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM

More information

Lecture 12 Circuits numériques (II)

Lecture 12 Circuits numériques (II) Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ual-well Trench-Isolated

More information

Review - Differential Amplifier Basics Difference- and common-mode signals: v ID

Review - Differential Amplifier Basics Difference- and common-mode signals: v ID 6.012 Microelectronic Devices and Circuits Lecture 20 DiffAmp Anal. I: Metrics, Max. Gain Outline Announcements Announcements D.P.: No Early effect in large signal analysis; just LECs. Lec. 21 foils useful;

More information

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model - Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next

More information

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions P. R. Nelson 1 ECE418 - VLSI Midterm Exam Solutions 1. (8 points) Draw the cross-section view for A-A. The cross-section view is as shown below.. ( points) Can you tell which of the metal1 regions is the

More information

ECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University

ECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University NAME: PUID: : ECE 305 Exam 5 SOLUTIONS: April 17, 2015 Mark Lundstrom Purdue University This is a closed book exam. You may use a calculator and the formula sheet at the end of this exam. Following the

More information

EE105 - Fall 2005 Microelectronic Devices and Circuits

EE105 - Fall 2005 Microelectronic Devices and Circuits EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture

More information

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;

More information

Long Channel MOS Transistors

Long Channel MOS Transistors Long Channel MOS Transistors The theory developed for MOS capacitor (HO #2) can be directly extended to Metal-Oxide-Semiconductor Field-Effect transistors (MOSFET) by considering the following structure:

More information

ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

More information

MOS CAPACITOR AND MOSFET

MOS CAPACITOR AND MOSFET EE336 Semiconductor Devices 1 MOS CAPACITOR AND MOSFET Dr. Mohammed M. Farag Ideal MOS Capacitor Semiconductor Devices Physics and Technology Chapter 5 EE336 Semiconductor Devices 2 MOS Capacitor Structure

More information

Lecture 16 The pn Junction Diode (III)

Lecture 16 The pn Junction Diode (III) Lecture 16 The pn Junction iode (III) Outline I V Characteristics (Review) Small signal equivalent circuit model Carrier charge storage iffusion capacitance Reading Assignment: Howe and Sodini; Chapter

More information

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

! CMOS Process Enhancements. ! Semiconductor Physics.  Band gaps.  Field Effects. ! MOS Physics.  Cut-off.  Depletion. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!

More information

ECE-305: Fall 2017 MOS Capacitors and Transistors

ECE-305: Fall 2017 MOS Capacitors and Transistors ECE-305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel Electrical and Computer Engineering Purdue

More information

HW 5 posted due in two weeks Lab this week Midterm graded Project to be launched in week 7

HW 5 posted due in two weeks Lab this week Midterm graded Project to be launched in week 7 HW 5 posted due in two weeks Lab this week Midterm graded Project to be launched in week 7 2 What do digital IC designers need to know? 5 EE4 EECS4 6 3 0< V GS - V T < V DS Pinch-off 7 For (V GS V T )

More information

Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET)

Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) Metal-Oxide-Semiconductor ield Effect Transistor (MOSET) Source Gate Drain p p n- substrate - SUB MOSET is a symmetrical device in the most general case (for example, in an integrating circuit) In a separate

More information

Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Chapter 2 CMOS Transistor Theory Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor Jin-Fu Li, EE,

More information

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 20, 2003

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 20, 2003 6.012 Microelectronic Devices and Circuits Spring 2003 Lecture 131 Lecture 13 Digital Circuits (II) MOS Inverter Circuits March 20, 2003 Contents: 1. NMOS inverter with resistor pullup (cont.) 2. NMOS

More information

Long-channel MOSFET IV Corrections

Long-channel MOSFET IV Corrections Long-channel MOSFET IV orrections Three MITs of the Day The body ect and its influence on long-channel V th. Long-channel subthreshold conduction and control (subthreshold slope S) Scattering components

More information

Biasing the CE Amplifier

Biasing the CE Amplifier Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC base-emitter voltage (note: normally plot vs. base current, so we must return to Ebers-Moll): I C I S e V BE V th I S e V th

More information

Section 12: Intro to Devices

Section 12: Intro to Devices Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si

More information

Lecture 7 PN Junction and MOS Electrostatics(IV) Metal Oxide Semiconductor Structure (contd.)

Lecture 7 PN Junction and MOS Electrostatics(IV) Metal Oxide Semiconductor Structure (contd.) Lecture 7 PN Junction and MOS Electrostatics(IV) Metal Oxide Semiconductor Structure (contd.) Outline 1. Overview of MOS electrostatics under bias 2. Depletion regime 3. Flatband 4. Accumulation regime

More information

II III IV V VI B C N. Al Si P S. Zn Ga Ge As Se Cd In Sn Sb Te. Silicon (Si) the dominating material in IC manufacturing

II III IV V VI B C N. Al Si P S. Zn Ga Ge As Se Cd In Sn Sb Te. Silicon (Si) the dominating material in IC manufacturing II III IV V VI B N Al Si P S Zn Ga Ge As Se d In Sn Sb Te Silicon (Si) the dominating material in I manufacturing ompound semiconductors III - V group: GaAs GaN GaSb GaP InAs InP InSb... The Energy Band

More information

ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)

ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view) ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 6: January 30, 2018 MOS Operating Regions, pt. 2 Lecture Outline! Operating Regions (review) " Subthreshold " Resistive " Saturation! Intro.

More information

EE 560 MOS TRANSISTOR THEORY

EE 560 MOS TRANSISTOR THEORY 1 EE 560 MOS TRANSISTOR THEORY PART 1 TWO TERMINAL MOS STRUCTURE V G (GATE VOLTAGE) 2 GATE OXIDE SiO 2 SUBSTRATE p-type doped Si (N A = 10 15 to 10 16 cm -3 ) t ox V B (SUBSTRATE VOLTAGE) EQUILIBRIUM:

More information

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis

More information

MOS Transistor Properties Review

MOS Transistor Properties Review MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO

More information

MOSFET Capacitance Model

MOSFET Capacitance Model MOSFET Capacitance Model So far we discussed the MOSFET DC models. In real circuit operation, the device operates under time varying terminal voltages and the device operation can be described by: 1 small

More information

Lecture 12: MOSFET Devices

Lecture 12: MOSFET Devices Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 2017 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2017 Khanna Lecture Outline! Semiconductor Physics " Band gaps "

More information

Electronic Devices and Circuits Lecture 14 - Linear Equivalent Circuits - Outline Announcements

Electronic Devices and Circuits Lecture 14 - Linear Equivalent Circuits - Outline Announcements 6.012 Electronic Devices and Circuits Lecture 14 Linear Equivalent Circuits Outline Announcements Handout Lecture Outline and Summary Review Adding refinements to large signal models Charge stores: depletion

More information

Problem 9.20 Threshold bias for an n-channel MOSFET: In the text we used a criterion that the inversion of the MOSFET channel occurs when V s = ;2 F w

Problem 9.20 Threshold bias for an n-channel MOSFET: In the text we used a criterion that the inversion of the MOSFET channel occurs when V s = ;2 F w Prof. Jasprit Singh Fall 2001 EECS 320 Homework 11 The nals for this course are set for Friday December 14, 6:30 8:30 pm and Friday Dec. 21, 10:30 am 12:30 pm. Please choose one of these times and inform

More information

ECE 305: Fall MOSFET Energy Bands

ECE 305: Fall MOSFET Energy Bands ECE 305: Fall 2016 MOSFET Energy Bands Professor Peter Bermel Electrical and Computer Engineering Purdue University, West Lafayette, IN USA pbermel@purdue.edu Pierret, Semiconductor Device Fundamentals

More information

N Channel MOSFET level 3

N Channel MOSFET level 3 N Channel MOSFET level 3 mosn3 NSource NBulk NSource NBulk NSource NBulk NSource (a) (b) (c) (d) NBulk Figure 1: MOSFET Types Form: mosn3: instance name n 1 n n 3 n n 1 is the drain node, n is the gate

More information

6.012 Electronic Devices and Circuits

6.012 Electronic Devices and Circuits Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless

More information

CHAPTER 5 MOS FIELD-EFFECT TRANSISTORS

CHAPTER 5 MOS FIELD-EFFECT TRANSISTORS CHAPTER 5 MOS FIELD-EFFECT TRANSISTORS 5.1 The MOS capacitor 5.2 The enhancement-type N-MOS transistor 5.3 I-V characteristics of enhancement mode MOSFETS 5.4 The PMOS transistor and CMOS technology 5.5

More information

The Devices: MOS Transistors

The Devices: MOS Transistors The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor

More information

Chapter 2 MOS Transistor theory

Chapter 2 MOS Transistor theory Chapter MOS Transistor theory.1 Introduction An MOS transistor is a majority-carrier device, which the current a conductg channel between the source and the dra is modulated by a voltage applied to the

More information

Department of Electrical and Computer Engineering, Cornell University. ECE 3150: Microelectronics. Spring Exam 1 ` March 22, 2018

Department of Electrical and Computer Engineering, Cornell University. ECE 3150: Microelectronics. Spring Exam 1 ` March 22, 2018 Department of Electrical and Computer Engineering, Cornell University ECE 3150: Microelectronics Spring 2018 Exam 1 ` March 22, 2018 INSTRUCTIONS: Every problem must be done in the separate booklet Only

More information

Electronic Devices and Circuits Lecture 15 - Digital Circuits: Inverter Basics - Outline Announcements. = total current; I D

Electronic Devices and Circuits Lecture 15 - Digital Circuits: Inverter Basics - Outline Announcements. = total current; I D 6.012 - Electronic Devices and Circuits Lecture 15 - Digital Circuits: Inverter asics - Outline Announcements Handout - Lecture Outline and Summary The MOSFET alpha factor - use definition in lecture,

More information

ECEN474/704: (Analog) VLSI Circuit Design Spring 2018

ECEN474/704: (Analog) VLSI Circuit Design Spring 2018 ECEN474/704: (Analog) SI Circuit Design Spring 2018 ecture 2: MOS ransistor Modeling Sam Palermo Analog & Mixed-Signal Center exas A&M University Announcements If you haven t already, turn in your 0.18um

More information

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering NAME: GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering ECE 4430 Third Exam Closed Book and Notes Fall 2002 November 27, 2002 General Instructions: 1. Write on one side of the

More information

EE115C Digital Electronic Circuits Homework #3

EE115C Digital Electronic Circuits Homework #3 Electrical Engineering Department Spring 1 EE115C Digital Electronic Circuits Homework #3 Due Thursday, April, 6pm @ 56-147E EIV Solution Problem 1 VTC and Inverter Analysis Figure 1a shows a standard

More information

VLSI Design and Simulation

VLSI Design and Simulation VLSI Design and Simulation CMOS Inverters Topics Inverter VTC Noise Margin Static Load Inverters CMOS Inverter First-Order DC Analysis R p V OL = 0 V OH = R n =0 = CMOS Inverter: Transient Response R p

More information

MOSFETs - An Introduction

MOSFETs - An Introduction Chapter 17. MOSFETs An Introduction Sung June Kim kimsj@snu.ac.kr http://helios.snu.ac.kr CONTENTS Qualitative Theory of Operation Quantitative I Relationships Subthreshold Swing ac Response Qualitative

More information

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. Refinement. Last Time. No Field. Body Contact

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. Refinement. Last Time. No Field. Body Contact ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 10: September 6, 01 MOS Transistor Basics Today MOS Transistor Topology Threshold Operating Regions Resistive Saturation

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler

More information

! MOS Capacitances. " Extrinsic. " Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications

! MOS Capacitances.  Extrinsic.  Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February, 07 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance Model!

More information

DC and Transient Responses (i.e. delay) (some comments on power too!)

DC and Transient Responses (i.e. delay) (some comments on power too!) DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02 - CMOS Transistor Theory & the Effects of Scaling

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 8: February 9, 016 MOS Inverter: Static Characteristics Lecture Outline! Voltage Transfer Characteristic (VTC) " Static Discipline Noise Margins!

More information

Spring Semester 2012 Final Exam

Spring Semester 2012 Final Exam Spring Semester 2012 Final Exam Note: Show your work, underline results, and always show units. Official exam time: 2.0 hours; an extension of at least 1.0 hour will be granted to anyone. Materials parameters

More information

Electronic Devices and Circuits Lecture 16 - Digital Circuits: CMOS - Outline Announcements (= I ON V DD

Electronic Devices and Circuits Lecture 16 - Digital Circuits: CMOS - Outline Announcements (= I ON V DD 6.01 - Electronic Deices and Circuits Lecture 16 - Digital Circuits: CMOS - Outline Announcements Handout; Web posting - Lecture Outline and Summary; two readings Exam - Wednesday, No. 5, 7:30-9:30 pm,

More information

6.012 Electronic Devices and Circuits

6.012 Electronic Devices and Circuits Page 1 of 1 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.12 Electronic Devices and Circuits Exam No. 1 Wednesday, October 7, 29 7:3 to 9:3

More information

EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR

EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR EE 23 Lecture 3 THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR Quiz 3 Determine I X. Assume W=u, L=2u, V T =V, uc OX = - 4 A/V 2, λ= And the number is? 3 8 5 2? 6 4 9 7 Quiz 3

More information

Midterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.

Midterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!

More information

EE 560 MOS TRANSISTOR THEORY PART 2. Kenneth R. Laker, University of Pennsylvania

EE 560 MOS TRANSISTOR THEORY PART 2. Kenneth R. Laker, University of Pennsylvania 1 EE 560 MOS TRANSISTOR THEORY PART nmos TRANSISTOR IN LINEAR REGION V S = 0 V G > V T0 channel SiO V D = small 4 C GC C BC substrate depletion region or bulk B p nmos TRANSISTOR AT EDGE OF SATURATION

More information

The Devices. Devices

The Devices. Devices The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ Field-Oxyde (SiO 2 ) p-substrate p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor Cross-Section of CMOS Technology MOS transistors

More information