ESE 570: Digital Integrated Circuits and VLSI Fundamentals


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1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 18: March 27, 2018 Dynamic Logic, Charge Injection
2 Lecture Outline! Sequential MOS Logic " DLatch " Timing Constraints! Dynamic Logic " Domino Logic! Charge Leakage! Charge Sharing! Domino Logic Design Considerations! Logic Comparisons 2
3 A Chip Example Penn ESE 570 Spring Khanna 3
4 Static CMOS TG DLATCH 8 Transistors 8 Transistors **Transistor level implementation using transmission gates requires fewer transistors 4
5 Static CMOS TG DLATCH CK D CK Q CK Q CK 5
6 Static CMOS TG DLATCH When CK = 1 output Q = D, and tracks D until CK = 0, the DLatch is referred to positive level triggered. When CK 1 to 0, the Q = D is captured, held (or stored) in the Latch. 6
7 CMOS D Edge Triggered FlipFlop Negative DLatch NMOS PMOS Positive DLatch Positive Edge Triggered D FlipFlop = Negative DLatch + Positive DLatch Negative Edge Triggered D FlipFlop = Positive DLatch + Negative DLatch 7
8 Impact of Nonideal Clock on DLatch Operation CLK ideal CLK nonideal CLK t CLK + τ D t NMOS PMOS CLK & CLK CLK & CLK + τ D 8
9 TwoPhase Clocked DLatch (nonoverlapping) ϕ 1 ϕ 1 ϕ 2 ϕ 2 t t ϕ 1 NMOS PMOS ϕ 1 ϕ 2 ϕ 2 9
10 Nonoverlapping Clocks! Play with in Cadence " Will need for project Penn ESE 570 Spring Khanna 10
11 Sequential Logic Timing Considerations Penn ESE 570 Spring Khanna 11
12 Timing Metrics Penn ESE 570 Spring Khanna 12
13 System Timing Constraints Penn ESE 570 Spring Khanna 13
14 Bistable Elements! The crosscoupling of two inverters results in a bistable circuit (a circuit with two stable states)! Have to be able to change the stored! Two approaches used " cutting the feedback loop (mux based latch) " overpowering the feedback loop (as used in SRAMs) Penn ESE 570 Spring Khanna 14
15 Mux Based Latches! Change the stored value by cutting the feedback loop Penn ESE 570 Spring Khanna 15
16 Tx Gate Implementation of Mux Penn ESE 570 Spring Khanna 16
17 PassT Implementation of Mux Penn ESE 570 Spring Khanna 17
18 Controller/Controlled ET Flip Flop Controller Controlled Penn ESE 570 Spring Khanna 18
19 Controller/Controlled Implementation Controller Controlled Penn ESE 570 Spring Khanna 19
20 Controller/Controlled Implementation Controller Controlled Controller transparent Controlled hold Controller hold Controlled transparent Penn ESE 570 Spring Khanna 20
21 Timing Properties! Assume propagation delays are t pd_inv and t pd_tx, and that the inverter delay to derive!clk is 0! Setup time  time before rising edge of clk that D must be valid " t su = 3 * t pd_inv + t pd_tx! Propagation delay  time for Q M to reach Q " t cq = t pd_inv + t pd_tx! Hold time  time D must be stable after rising edge of clk " t hold = zero Penn ESE 570 Spring Khanna 21
22 Setup Time Simulation Penn ESE 570 Spring Khanna 22
23 Setup Time Simulation Penn ESE 570 Spring Khanna 23
24 System Timing Constraints Penn ESE 570 Spring Khanna 24
25 Dynamic Logic 25
26 Logic Comparison Overview DYNAMIC LOGIC GATES: valid logic level are not steadystate op points and depend on temporary storage of charge on parasitic node capacitances. Outputs are generated in response to input voltage levels and a clock. Requires periodic updating or refresh. 26
27 Logic Comparison Overview bit bit_b word N2 P1 P2 N4 A N1 N3 A_b WL C BL BL M1 C S DYNAMIC LOGIC GATES: valid logic level are not steadystate op points and depend on temporary storage of charge on parasitic node capacitances. Outputs are generated in response to input voltage levels and a clock. Requires periodic updating or refresh. 27
28 Comparison of Logic Implementations Y Ratioed 28
29 Comparison of Logic Implementations Y Ratioed 29
30 Comparison of Logic Implementations Y Ratioed 30
31 Comparison of Logic Implementations Y Ratioed V DD 1 more robust
32 Dynamic CMOS Precharge V DD CK A M p M e Z 32
33 Dynamic CMOS Precharge Z Z of C is complete 33
34 Dynamic (Clocked) Logic: Example CK = 0 => Z =? CK = 1 => Z =? 34
35 Comparison of Static and Dynamic Logic ADVANTAGES? DISADVANTAGES? 35
36 Comparison of Static and Dynamic Logic 36
37 Comparison of Static and Dynamic Logic 37
38 Cascaded Dynamic Logic 38
39 Cascaded Dynamic Logic 39
40 Cascaded Dynamic Logic 40
41 Cascaded Dynamic Logic 41
42 Domino Logic 42
43 Requirements! Single transition " Once transitioned, it is done # like domino falling! All inputs at 0 during precharge " Outputs precharged to 1 then inverted to 0 " I.e. Inputs are precharge to 0! Noninverting gates 43
44 Cascaded Domino CMOS Logic Gates 44
45 Cascaded Domino CMOS Logic Gates propagating 45
46 Cascaded Domino CMOS Logic Gates propagating 46
47 Charge Leakage
48 CMOS Dynamic D Latch D Positive levelsensitive Q C x is usually a parasitic capacitance NMOS PMOS 48
49 Comparison CMOS Static & Dynamic DLatch Static DLatch ϕ 1 ϕ 1 Data bit stored in bistableloop when ϕ 1 = 1 0 NMOS PMOS Dynamic D Latch Data bit stored on C x when CK =
50 Latch circuit: NOTE: No crosscoupled inverters) FlipFlop Latch 50
51 51
52 52
53 V y V T0n,M3 = 1.0 V; V y = V T0n = 1V (V GD > V T0p ) 53
54 V y V T0n,M3 = 1.0 V; V y = V T0n = 1V (V GD > V T0p ) 54
55 V y V T0n,M3 = 1.0 V; V y = V T0n = 1V (V GD > V T0p ) 55
56 V y V T0n,M3 = 1.0 V; V y = V T0n = 1V (V GD > V T0p ) i.e. V x can drop from V xmax = V DD V TMP to V xmin = 2.55 V due to charge leakage before V Q is effected (i.e. the output changes state). 56
57 Charge Storage and Leakage! Assume logichigh is stored onto V x during active phase (CK=1)! When CK=0, V in #0 57
58 Charge Storage and Leakage 58
59 Charge Storage and Leakage interconnect C ext C ext 59
60 Junction Capacitance C ext C ext I leakage = C x dv x dt 60
61 Junction Capacitance C ext C ext I leakage = C x dv x dt ESTIMATE V xmax to V xmin due to leakage. 61
62 Junction Capacitance C ext C ext I leakage = C x dv x dt ESTIMATE V xmax to V xmin due to leakage. min(t hold ) = Δt = C x min I leakage max ΔV x = C x min I leakage max (V x max V x min ) 62
63 Junction Capacitance C ext C ext I leakage = C x dv x dt ESTIMATE V xmax to V xmin due to leakage. min(t hold ) = Δt = C x min I leakage max ΔV x = C x min I leakage max (V x max V x min ) V x max = V DD V Tn,MP V x min = 2.55V C x min = C ext + C j,min = C ext + C j (V = V x max ) 63
64 Example V xmax. Assume V DD leakagemax V x max = V DD V Tn,MP V x min = 2.55V 64
65 Example C n+p+ = CJSW P n+p+ = ff/µm (18 µm + 6 µm + 2 µm) = 5.20 ff C n+p = CJ A n+p = ff/µm 2 (36 µm µm 2 ) = 4.56 ff 65
66 Example min(t hold ) = Δt = C x min I leakage max ΔV x = C x min I leakage max (V x max V x min ) C x min = C ext + C j,min = C ext + C j (V = V x max ) 66
67 Example min(t hold ) = Δt = C x min I leakage max ΔV x = C x min I leakage max (V x max V x min ) VDD = 5.0 V VT0 = 1.0 V PB = 0.88 V PBsw = 0.95 V I leakage,max = 0.85 pa C x min = C ext + C j,min = C ext + C j (V = V x max ) V x max = V DD V Tn,MP 4V V x min = 2.55V 67
68 Example min(t hold ) = Δt = C x min I leakage max ΔV x = C x min I leakage max (V x max V x min ) VDD = 5.0 V VT0 = 1.0 V PB = 0.88 V PBsw = 0.95 V I leakage,max = 0.85 pa C x min = C ext + C j,min = C ext + C j (V = V x max ) V x max = V DD V Tn,MP 4V V x min = 2.55V C j (V ) = A C j0 1+ V φ 0 + P C j0sw 1+ V φ 0sw C j (V x max = 4V ) = 4.56 ff 1+ 4V ff 1+ 4V 0.95 = 4.21fF 68
69 Example min(t hold ) = Δt = C x min I leakage max ΔV x = C x min I leakage max (V x max V x min ) VDD = 5.0 V VT0 = 1.0 V PB = 0.88 V PBsw = 0.95 V I leakage,max = 0.85 pa C x min = C ext + C j,min = C ext + C j (V = V x max ) C x min = 0.52 ff ff ff fF = 8.05 ff 69
70 Example min(t hold ) = Δt = C x min I leakage max ΔV x = C x min I leakage max (V x max V x min ) VDD = 5.0 V VT0 = 1.0 V PB = 0.88 V PBsw = 0.95 V I leakage,max = 0.85 pa C x min = C ext + C j,min = C ext + C j (V = V x max ) C x min = 0.52 ff ff ff fF = 8.05 ff min(t hold ) = 8.05 ff (4V 2.55V ) =13.73ms 0.85pA 70
71 Example Overview: Min Hold Time! Find min voltage value for storage node to maintain data " V x = voltage across storage capacitor! With dimensions of switch MOS and load MOS " Calculate C ext = C gb + C int = C gb + C poly + C metal " Calculate C j = junction capacitance! With max leakage value " Calculate min hold time (i.e. min time for storage capacitor to leak to min V x ) min(t hold ) = Δt = C x min I leakage max ΔV x = C x min I leakage max (V x max V x min ) Penn ESE 570 Spring Khanna 71
72 Charge Sharing
73 Dynamic Circuit Techniques 73
74 Shift Register! Shift registers store and delay data! Simple design: cascade of latches D D Latch ϕ 2 D Latch ϕ 1 ϕ 1 D Latch Out 74
75 Shift Register with Dynamic D Latches When V out(i) = 0V (or 5V) and V in(i+1) = 5V (or 0V) for i = 1,2 (stage) Charge Sharing is an issue when ϕ 1 /ϕ 2 close. 75
76 Charge Sharing V b >> V a 76
77 Charge Sharing V b >> V a 77
78 Charge Sharing Rule of Thumb make C out1 = 10 C in2 V b >> V a 78
79 Charge Sharing V b << V a 79
80 Charge Sharing V b << V a If V b = 0 and V a >> V b # V R C in2v DD C out1 + C in2 80
81 Charge Sharing V b << V a If V b = 0 and V a >> V b # V R C in2v DD C out1 + C in2 If C out1 >> C in2 # V R C in2v DD C out1 << V DD 81
82 Charge Sharing Rule of Thumb make C out1 = 10 C in2 V b << V a If V b = 0 and V a >> V b # V R C in2v DD C out1 + C in2 If C out1 >> C in2 # V R C in2v DD C out1 << V DD 82
83 Shift Register with Dynamic D Latches m 83
84 Domino Logic Design Considerations
85 Requirements! Single transition " Once transitioned, it is done # like domino falling! All inputs at 0 during precharge " Outputs precharged to 1 then inverted to 0 " I.e. Inputs are precharge to 0! Noninverting gates 85
86 Cascaded Domino CMOS Logic Gates propagating 86
87 Precharge Leakage weak keeper (W/L) pkeeper < (W/L) nmin 87
88 Charge Sharing within PDN 88
89 Charge Sharing within PDN 89
90 Charge Sharing within PDN 90
91 Charge Sharing within PDN Since all nodes are precharged there is no chargesharing. C 4 Z4 Z3 C 3 C 2 Z2 Z1 P0 C 1 Z1 = G1 + P1 * P0 Z2 = G2 + P2 * G1 + P2 * P1 * P0 = G2 + P2 * Z1 Z3 = G3 + P3 * G2 + P3 * P2 * G1 + P3 * P2 * P1 * P0 = G3 + P3 * Z2 Z4 = G4 + P4 * G3 + P4 * P3 * G2 + P4 * P3 * P2 * G1 + P4 * P3 *P1 * P0 = G4 + P4 * Z3 91
92 CMOS Logic! Best option in the majority of CMOS circuits! Advantages: " Noiseimmunity not sensitive to k n /k p " does not involve precharging of nodes " dissipates no DC power " layout can be automated! Disadvantages: " Large fanin gates lead to complex circuit structures (2N transistors) " larger parasitics " slower and higher dynamic power dissipation than alternatives " no clock and no synchronization. 92
93 PseudonMOS/Ratioed Logic! Finds widest utility in large fanin gates! Advantages: " Requires only N+1 transistors for N fanin " smaller parasitics " faster and lower dynamic power dissipation than full CMOS! Disadvantages: " Noiseimmunity sensitive to k n /k p " dissipates DC power when pulled down " not wellsuited for automated layout " no clock and no synchronization. 93
94 CMOS dominologic! Used for lowpower, highspeed applications.! Advantages: " Requires N+k transistors for N fanin (size advantages of pseudonmos) " dissipates no DC power " noise immunity not sensitive to k n /k p " use of clocks enables synchronous operation! Disadvantages: " Relies on storage on soft nodes " will require thorough simulation at all the process corners to insure proper operation " some of the speed advantage over static gates is diminished by the required precharge (predischarge) time 94
95 Ideas! Leads to clocked circuit discipline " Uses state holding element (eg. Latches and registers) " Prevents timing assumptions and complex reasoning about all possible timings! Dynamic/clocked logic " Only build/drive one pulldown network " Fast transition propagation! Domino Logic allows for cascading! Charge Leakage " Constrains maximum clock frequency! Charge Sharing with pass gates " Need to size carefully! Different logictypes for different applications 95
96 Admin! HW 7 out now " Due midnight " Start now. Involves optimization, which takes time.! Start getting groups together for project " Groups of 2 96
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