ESE 570: Digital Integrated Circuits and VLSI Fundamentals


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1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 6: January 30, 2018 MOS Operating Regions, pt. 2
2 Lecture Outline! Operating Regions (review) " Subthreshold " Resistive " Saturation! Intro. to Scaling! Short channel effects " Velocity Saturation " Drain Induced Barrier Lowering " V th 3
3 Review: nmos IV Characteristics I D = I S W L e V GS V th nkt /q 1 e V DS kt /q 1+ λv DS µ n C ox W 2 L 2 ( V V (V ) GS Tn SB )V DS V 2 DS µ n C ox 2 ( ) V GS V Tn Subthreshold ( ) (1+ λ V DS ) V GS >V Tn,V DS <V GS Linear W L V GS V Tn (V SB ) ( ) 2 (1+ λ V DS ) V GS >V Tn,V DS V GS V Tn Saturation 4
4 Review: pmos IV Characteristics I D = I S W L e V GS V th nkt /q 1 e V DS kt /q 1+ λv DS µ n C ox W 2 L 2 ( V V (V ) GS Tn SB )V DS V 2 DS µ n C ox 2 ( ) V GS V Tp Subthreshold ( ) (1+ λ V DS ) V GS <V Tp,V DS >V GS Linear W L V GS V Tn (V SB ) ( ) 2 (1+ λ V DS ) V GS <V Tp,V DS V GS V Tp Saturation 5
5 Effective Channel Length and Width n + n + L eff = L M 2LD DL W eff = W M DW DL and DW: error in photolithography and etching 6
6 Scaling
7 Scaling! Premise: features scale uniformly " everything gets better in a predictable manner! Parameters: # λ (lambda)  Mead and Conway # F  Half pitch ITRS (F=2λ) # S scale factor # F =F/S 8
8 Half Pitch Definition Metal Pitch Poly Pitch (Typical DRAM) (Typical MPU/ASIC) Source: 2001 ITRS  Exec. Summary, ORTC Figure, Andrew Kahng 9
9 MOS Transistor Scaling  (1974 to present) S=1.5 $ 1/S = 0.7 per technology node [1/S 2 =0.5 per 2 nodes] Pitch Gate Source: 2001 ITRS  Exec. Summary, ORTC Figure, Andrew Kahng 10
10 Scaling Calculator + Node Cycle Time: Log HalfPitch 1994 NTRS .7x/ 3yrs Actual .7x/2yrs 0.7x 0.7x Linear Time 250 > 180 > 130 > 90 > 65 > 45 > 32 > 22 > x N N+1 N+2 Source: 2001 ITRS  Exec. Summary, ORTC Figure, Andrew Kahng 11
11 MOSFET Scaling! First order constant field scaling (aka full scaling/ ideal scaling) " Electric field, E, is kept constant by reducing dimensions of device by scale factor S " All dimensions (1/S), voltages (1/S), and doping concentrations (S) are scaled 12
12 Alternative MOSFET Scaling! Constant Voltage Scaling " VDD is kept constant while reducing dimensions of device by scale factor S " All dimensions (1/S) and doping concentrations (S) are scaled! Lateral Scaling " Only the gate length dimension is scaled (1/S) 13
13 Influence of Scaling S=α PERFORMANCE Wire Delay (T)  R wire C wire
14 Influence of Scaling S=α PERFORMANCE Wire Delay (T)  R wire C wire
15 Power Dissipation (Dynamic)! Capacitive (Dis)charging scaling?! P=(1/2)CV 2 f! V$ V/S! C $ C/S! P$ P/S 3 Penn ESE 570 Spring Khanna 16
16 Power Dissipation (Dynamic)! Capacitive (Dis)charging with ideal scaling?! P=(1/2)CV 2 f! Increase Frequency?! V$ V/S! C $ C/S! P$ P/S 3! τ gd $ τ gd /S! So: f $ f S! P $ P/S 2 Penn ESE 570 Spring Khanna 17
17 Influence of Scaling S=α PERFORMANCE Wire Delay (T)  R wire C wire
18 Power Dissipation (Dynamic)! Capacitive (Dis)charging with constant voltage scaling?! P=(1/2)CV 2 f! Increase Frequency?! V$ V! C $ C/S! P$ P/S! τ gd $ τ gd /S 2! So: f $ f S 2! P $ P*S Penn ESE 570 Spring Khanna 19
19 Influence of Scaling S=α PERFORMANCE Wire Delay (T)  R wire C wire
20 Power Dissipation (Dynamic)! Capacitive (Dis)charging with constant voltage scaling?! P=(1/2)CV 2 f! Increase Frequency?! V$ V! τ gd $ τ gd /S 2! C $ C/S! So: f $ f S 2! P$ P/S! P $ P*S If don t scale V, power dissipation doesn t scale down! Penn ESE 570 Spring Khanna 21
21 And Power Density! P$ P S (increase frequency)! But Α $ Α/S 2! What happens to power density?! P/A $ S 3 P! Power Density Increases!! Penn ESE 570 Spring Khanna 22
22 Influence of Scaling S=α PERFORMANCE Wire Delay (T)  R wire C wire
23 Historical Voltage Scaling Solution: scale voltage separately from S " Power and frequency increase less Penn ESE 570 Spring Khanna 24
24 uproc Clock Frequency MHz The Future of Computing Performance: Game Over or Next Level? National Academy Press, 2011 Penn ESE 570 Spring Khanna 25
25 up Power Density Watts The Future of Computing Performance: Game Over or Next Level? National Academy Press, 2011 Penn ESE 570 Spring Khanna 26
26 Short Channel Effects 27
27 Primer! What is electrical field in channel?! Velocity:! Electron mobility: L eff = 25nm,V DS =1V Field = V DS L eff v = F µ n! What is electron velocity? µ n = 500cm 2 / (V s) 28
28 Moving Charge! I = 1 $ # &V " R %! I increases linearly in V Field = V DS L eff, v = µ n F v = µ V " DS = µ n L $ eff # L eff % ' V DS &! Velocity increases linearly in V! What s I? " ΔQ/Δt " Speed at which charge moves! What s a moving electron? 29
29 Short Channel! Model assumes carrier velocity increases with field " Increases with voltage 30
30 Short Channel! Model assumes carrier velocity increases with field " Increases with voltage (3x10 8 m/sec) 31
31 Short Channel! Velocity saturates for decreasing channel length and increasing field 32
32 Short Channel! Model assumes carrier velocity increases with field " Increases with voltage! There is a limit to how fast carriers can move " Limited by scattering effects " ~ 10 5 m/s! Encounter velocity saturation when channel short " Modern processes, L is short enough to reach this region of operation 33
33 Velocity Saturation! At what voltage do we hit the speed limit? " V dsat = voltage at which velocity (current) saturates Field = V DS L eff, v = µ n F v = µ V " DS = µ n L $ eff # L eff % ' V DS & L eff = 25nm,V DS =? Field = V DS L eff µ n = 500cm 2 / (V s) 34
34 Velocity Saturation! Once velocity saturates: W I DS = µ n C OX ( V L GS V th )V DS V 2 DS 2 V I DS = µ DS n C L OX W ( V GS V ) th V DS 2 V V DS =V dsat I DS = µ dsat n C L OX W V GS V th V dsat Lv sat I µ DS v sat C OX W V GS V th n ( ) V dsat ( ) V dsat
35 Velocity Saturation! Once velocity saturates: W I DS = µ n C OX ( V L GS V th )V DS V 2 DS 2 V I DS = µ DS n C L OX W ( V GS V ) th V DS 2 V V DS =V dsat I DS = µ dsat n C L OX W V GS V th V dsat Lv sat I µ DS v sat C OX W V GS V th n ( ) V dsat ( ) V dsat
36 Velocity Saturation! Once velocity saturates: Mobility degradaion due to lateral electric field (V DS /L eff ) 37
37 Velocity Saturation! Long Channel! Short Channel 38
38 Velocity Saturation I D V DS 39
39 Velocity Saturation! Once velocity saturates we can still increase current with parallelism " Effectively make a wider device 40
40 Short Channel! Mobility degradation due to high normal electric field " High gatetosource voltage µ n (eff ) µ n0 1+θ(V GS V T ) " θ= mobility modulation factor (empirical) 41
41 Threshold 42
42 Short Channel  Threshold S G D S G D n+ n+ pn+ depletion region Q B0 L eff V GS induced depletion region pn+ depletion region x j n+ n+ L eff Q B0(sc) V T0 (short channel) = V T0  ΔV T0 43
43 Short Channel  Threshold S G D S G D n+ n+ pn+ depletion region Q B0 L eff V GS induced depletion region pn+ depletion region x j n+ n+ L eff Q B0(sc) V T0 (short channel) = V T0  ΔV T0 44
44 Short Channel  Threshold Penn ESE 570 Spring Khanna 45
45 Short Channel  Threshold Penn ESE 570 Spring Khanna 46
46 Threshold Example! Consider an nchannel MOS process with the following parameters: N A = cm 3, N D (gate) = 2x10 20 cm 3, t ox = 50 nm, N ox = 4x10 10 cm 2,and N D (S/D) = cm 3. In addition, the channel region is implanted with ptype impurities (impurity concentration N I = 2 x cm 2 ) to adjust the threshold voltage. The junction depth of the source and drain diffusion regions is x j = 1.0 um.! Plot the variation of the zerobias threshold voltage V T0 as a function of the channel length (assume that V DS = V SB = 0). Penn ESE 570 Spring Khanna 47
47 Threshold Example Penn ESE 570 Spring Khanna 48
48 Threshold! Describe V T as a constant! Induce enough electron collection to invert channel 49
49 V DS impact! In practice, V DS impacts state of channel 50
50 V DS impact! Increasing V DS, already depletes portions of channel 51
51 V DS impact! Increasing V DS, already depletes portions of channel! Need less charge, less voltage to create inversion layer 52
52 DrainInduced Barrier Lowering (DIBL) V T V DS 53
53 Threshold Example! Consider an nchannel MOS process with the following parameters: N A = cm 3, N D (gate) = 2x10 20 cm 3, t ox = 50 nm, N ox = 4x10 10 cm 2,and N D (S/D) = cm 3. In addition, the channel region is implanted with ptype impurities (impurity concentration N I = 2 x cm 2 ) to adjust the threshold voltage. The junction depth of the source and drain diffusion regions is x j = 1.0 um.! Plot the variation of the zerobias threshold voltage V T0 as a function of the channel length (assume that V DS = V SB = 0).! Also find V T0 for L = 0.7 um, V DS = 5 V, and V SB = 0. Penn ESE 570 Spring Khanna 54
54 Review: nmos IV Characteristics I D = I S W L e V GS V th nkt /q 1 e V DS kt /q 1+ λv DS µ n C ox W 2 L 2 ( V V (V ) GS Tn SB )V DS V 2 DS µ n C ox W 2 L V V (V ) GS Tn SB v sat C OX W V GS V th 2 ( ) V GS V Tn Subthreshold ( ) (1+ λ V DS ) V GS >V Tn,V DS <V GS Linear ( ) 2 (1+ λ V DS ) V GS >V Tn,V DS V GS V Tn Saturation ( ) V dsat E y > E cn (short channel) Velocity Saturation 55
55 Review: pmos IV Characteristics I D = I S W L e V GS V th nkt /q 1 e V DS kt /q 1+ λv DS µ n C ox W 2 L 2 ( V V (V ) GS Tn SB )V DS V 2 DS µ n C ox W 2 L V V (V ) GS Tn SB v sat C OX W V GS V th 2 ( ) V GS V Tp Subthreshold ( ) (1+ λ V DS ) V GS <V Tp,V DS >V GS Linear ( ) 2 (1+ λ V DS ) V GS <V Tp,V DS V GS V Tp Saturation ( ) V dsat E y > E cp (short channel) Velocity Saturation 56
56 SPICE/Cadence Models! Level 1 Analytical model, I D (sat) is described by square with Channel Length Modulation. Based on GCA (gradual channel approximation) equations! Level 2  Analytical model, includes second order effects, e.g. mobility degradation, small channel effect an subthreshold currents. Relaxes some GCA assumptions! Level 3 semiempirical model, uses simpler equations than level 2 plus empirical equations fit to experimental data. Improves accuracy and reduces simulation/solver time! BSIM3 (Berkeley ShortChannel IGFET MODEL) includes submicron MOSFET characteristics. Analytically simple, makes full use of parameters extracted from experimental data 57
57 Complexity of SPICE Models vs. Time SPICE Parameter Calculator Rochester Institute of Technology 58
58 MOS SPICE Model Parameters Name LEVEL Model Parameters Model type (1, 2, or 3) Units L Channel length (designer input) m W Channel width (designer input) m LD Lateral diffusion length m WD Lateral diffusion width m VTO Zerobias threshold voltage V U0 Mobility cm**2/vs KP Transconductance A/V**2 GAMMA Bulk threshold parameter V**1/2 PHI Surface potential V LAMBDA Channellength modulation 1/V (LEVEL = 1 and 2) RD Drain ohmic resistance Ohms RS Source ohmic resistance Ohms RG Gate ohmic resistance Ohms RB Bulk ohmic resistance Ohms RDS Drainsource shunt resistance Ohms RSH Drainsource diffusion sheet Ohms/sq. Resistance NRS Number of squares of RD, RS IS Bulk pn saturation current A JS PB Bulk pn saturation/current area Bulk pn potential A/m**2 V 59
59 MOS SPICE Model Parameters Name LEVEL Model Parameters Model type (1, 2, or 3) Units CBD Bulkdrain zerobias pn cap (not used) F CBS Bulksource zerobias pn cap (not used) F CJ Bulk pn zerobias bottom cap/area F/m**2 CJSW Bulk pn zerobias perimeter cap/length F/m MJ Bulk pn bottom grading coefficient MJSW Bulk pn sidewall grading coefficient FC Empirical bulk pn forwardbias cap coefficient CGSO Gatesource overlap cap/channel width F/m CGDO Gatedrain overlap cap/channel width F/m CGBO Gatebulk overlap cap/channel width F/m NSUB Substate doping density 1/cm**3 NSS NFS Surfacestate density Fast surfacestate density 1/cm**2 1/cm**2 TOX Oxide thickness m TPG Gate material type: + 1 = opposite of substrate,  1 = same as substrate, 0 = aluminum XJ Metallurgical junction depth m 60
60 MOS SPICE Model Parameters Name LEVEL Model Parameters Model type (1, 2, or 3) Units UCRIT Mobility degradation critical field V/cm (LEVEL=2) UEXP Empirical mobility degradation exponent (LEVEL=2) VMAX Maximum carrier drift velocity (Level=2) m/s NEFF Empirical channel charge coefficient (LEVEL=2) XQC Empirical Fraction of channel charge attributed to drain (Level=2) DELTA THETA Empirical channel width effect on V T Empirical mobility modulation (LEVEL=3) 1/V ETA KAPPA Empirical static feedback on V T (LEVEL=3) Empirical saturation field factor (LEVEL=3) KF AF Flicker noise coefficient Flicker noise exponent 61
61 Big Idea! 4 Regions of operation for MOSFET " Subthreshold " Linear " Saturation " Pinch Off " Channel length modulation " Velocity Saturation " Short channel effects! Different level Models for Theory of Operation 62
62 Admin! HW 3 due Thursday, 2/1 63
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