Chapter 5 MOSFET Theory for Submicron Technology


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1 Chapter 5 MOSFET Theory for Submicron Technology Short channel effects Other small geometry effects Parasitic components Velocity saturation/overshoot Hot carrier effects ** Majority of these notes are courtesy of Prof. Edwin Kan at Cornell University Chapter 5 1
2 MOSFET ShortChannel Effects on V th Three MITs of the Day Shortchannel effects (SCE) viewing from potential contours and from lateral field penetration Shortchannel effects with respect to diode charge Shortchannel effects with respect to drain bias (DIBL) (Bonus): possible origins of reverse short channel effects Reading assignment: Taur & Ning Sections Chapter 5 2
3 MOSFET Correction from Submicron Geometry All corrections we have discussed until now apply to longchannel MOSFET, where the source/drain diodes, series resistance, parasitic capacitance and isolation structure are not considered in the PaoSah model. It seems that there is a MOSC box under the gate oxide (the holy box ) where all charge analyses are performed (GCA). However, any potential or charge effect that will touch or affect the shape of the holy box will affect the threshold voltage for submicron MOSFETs. S B D n + n + GCA dictates: 2 ψ >> 2 2 x y W dm The holy box 2 ψ x y in the holy box Chapter 5 3
4 Threshold Voltage is Most Critical for Circuit Behavior and Process Control V th marks the V GS when the channel is switching from OFF to ON. In linear scale of I D, this is the extrapolation point from the maximum slope of I D (V GS ) due to mobility reduction at high V GS In log scale of I D, this is the point where the channel current changes from exponential dependence on V GS to superlinear dependence on V GS. To guarantee homogeneous behavior of transistor across the chip, V th usually needs to have less than 0.07V variation for 3σ devices. linear I D Chapter 5 4 log I D low V DS low V DS V th V th maximum slope above V th V GS 3dB or 2 times smaller in magnitude V GS correction on V th for even just 0.1V may lead to channel current variation of e 0.1q/KT 45 times at room temperature!!!
5 Shortchannel V th Rolloff Viewing from Potential Contours V th SCE, small V DS long channel; GCA good SCE, large V DS L eff Potential contours from numerical simulation short channel; 2D potential necessary Chapter 5 5
6 SCE from Diodecharge Sharing View ΔV V V th( SCE ) th( long ) th( short ) operational definition There are several physical effects arising from the short channel geometry. We will first discuss SCE strictly from the geometry of static charge sharing of the source/drain diodes. Apparently within the edge of the S/D junctions, not all of the charges are controllable by MOSC V GS systems. Part of the junction charge is controlled by the S/B and D/B diodes. Portion of charge controlled by the S/B and D/B diodes x p r j diode slice L eff MOSC slice W dm diode slice W (into the paper) x p Chapter 5 6
7 ΔV th Diodecharge Sharing Formalism qn AW r dm j 2Wdm ( diode) = ( 1+ 1) C L r ox eff j The above equation involves serious assumptions (without those, only device simulation possible for calculation including detailed geometry): perfect geometry and doping (round shape of source/drain, uniform substrate, abrupt junction; x p = W dm ) arbitrary partition of charges V DS can be considered by modifying x p, but there are other effects. To minimize (ΔV th(diode) /V th ): r j Shallow junction depth. Limited by source sheet resistance. N A t ox Chapter 5 7 No V BS L r eff j 0 ΔV ΔV th( diode th( diode) ) 0 0 N A W dm canceling each other in the prefactor, but the square root term will be smaller with larger N A (smaller W dm ). Limited by bandtoband tunneling Increase C ox. It helps by increasing the gate control. scale t ox more aggressively than others Reversebias V BS enhances SCE
8 DrainInduced Barrier Lowering (DIBL) In a crude approximation, there is more depletion region at the drain when V DS >0. Therefore, the charge not controllable by V GS at the drain end should be larger for SCE analysis. This is what has been included in the SPICE level 2 model. However, this is NOT enough and cannot account for the strong L eff dependence of V th when channel length is smaller than 0.3μm A sufficient accuracy can only be obtained from the 2D Poisson equations, since DIBL is really caused by the pulldown of source potential barrier by V DS. Apparently if the channel is long enough, the channel charge decouples the source barrier from V DS (as in our subthreshold analysis in subthreshold) Chapter 5 8 r j Leff W dm
9 Potential Curvature at the Source Barrier φ S L eff long channel source barrier short channel V DS Δ Vth( DIBL) σv DS The source barrier is pulled down by V DS, if L eff is very short and V DS is very large change in V th for short L and possible change in S if subthreshold measurement is done with large V DS (in severe cases, device with short L can never be turned off with large V DS ). 2D device simulation is usually necessary, or a common phenomenological expression (such as that in BSIM3v3) is V th =V th0 σv DS is used. DIBL is not all bad, since it does gives larger ON current when there is a V DS. DIBL gives aggressive scaling of V DD some extra freedom. Chapter 5 9
10 Parametric Dependence of DIBL I D with DIBL ignore DIBL logi D with DIBL and large V DS ignore DIBL or small V DS V DS V GS If V DS increases, DIBL increases If L eff decreases, DIBL increases (almost exponential dependence). If t ox decreases, DIBL decreases (gate has more control) If r j decreases, DIBL decreases (less V DS coupling to source barrier) if V BS more reverse biased, DIBL increases (additional depletion charge helps couple the drain and source potential) Chapter 5 10
11 Quantitative Treatment of SCE on ΔV th from Lateral Field Penetration The previous diodecharge sharing and potential contours are easy to understand physical concepts, but too many assumptions are necessary to arrive at reasonable closeform expression. Usually the 2D potential effects are simulated VERY carefully with device simulation (distributive finite element) in technology development. Inaccurate, but acceptable design equations are still VERY useful in initial device design phase. The Poisson equation relates: potential curvature with the net charge electric field gradients with the net charge We are most interested around V th (or a bit below V th where the net charge is basically the bulk dopant charge), and the lateral field penetration can give very useful design insights semiquantitatively. Chapter 5 11
12 DIBL Viewed by Lateral Field Penetration log(f y ) at low V DS Lateral Field Penetration Debye length of the substrate as the exponential decay log(f y ) at high V DS ε si ε ΔV 0 th Fx = ρ ε siε 0 x 24tox = ψ bi W e πl dm eff / 2 ( W + 3t ) dm ( ψ + V ) ox F bi y y DS Chapter 5 12
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