S=0.7 [0.5x per 2 nodes] ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. Scaling ITRS Roadmap

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1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 15: October 4, 2013 Scaling Today VLSI Scaling Trends/Disciplines Effects Alternatives (cheating) 1 2 Scaling ITRS Roadmap Premise: features scale uniformly everything gets better in a predictable manner Parameters: λ (lambda) -- Mead and Conway (Day14) F -- Half pitch ITRS (F=2λ) S scale factor Rabaey F =S F 3 Semiconductor Industry rides this scaling curve Try to predict where industry going (requirements self fulfilling prophecy) 4 Preclass 1 Scaling from 32nm 22nm? MOS Transistor Scaling (1974 to present) S=0.7 [0.5x per 2 nodes] Pitch Gate 5 Source: 2001 ITRS - Exec. Summary, ORTC Figure [from Andrew Kahng] 6 1

2 Half Pitch (= Pitch/2) Definition Metal Pitch Poly Pitch Scaling Calculator + Cycle Time: 0.7x 0.7x Node 250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16 Log Half-Pitch 1994 NTRS -. 7x/3yrs Actual -.7x/2yrs Linear Time 0.5x N N+1 N+2 Node Cycle Time (T yrs): *CARR(T) = (Typical DRAM) Source: 2001 ITRS - Exec. Summary, ORTC Figure (Typical MPU/ASIC) [from Andrew Kahng] 7 [(0.5)^(1/2T yrs)] - 1 * CARR(T) = Compound Annual CARR(3 yrs) = -10.9% Reduction Rate (@ cycle time period, T) CARR(2 yrs) = -15.9% Source: 2001 ITRS - Exec. Summary, ORTC Figure [from Andrew Kahng] 8 Scaling Channel Length (L) Channel Width (W) Oxide Thickness (T ox ) Doping (N a ) Voltage (V) Full Scaling Channel Length (L) Channel Width (W) Oxide Thickness (T ox ) S S S Doping (N a ) 1/S Voltage (V) S 9 10 Effects on Physical Properties? Area Capacitance Resistance Threshold (V th ) Current (I d ) Gate Delay (τ gd ) Wire Delay (τ wire ) Power Go through full (ideal) then come back and ask what still makes sense today. 11 λ λs Area impact? Α = L W Α ΑS 2 Area S=0.7 [0.5x per 2 nodes] Pitch 32nm 22nm 50% area 2 capacity same area L Gate W 12 2

3 Capacity Scaling from Intel Capacitance Capacitance per unit area C ox = ε SiO 2 /T ox T ox S T ox C ox C ox /S Capacitance Resistance Gate Capacitance C gate = A C ox Α Α S 2 C ox C ox /S C gate S C gate Resistance R=ρL/(W*t) W S W L, t similar R R/S Threshold Voltage Current V TH S V TH Saturation Current I d =(µc OX /2)(W/L)(V gs -V TH ) 2 V gs= V S V V TH S V TH W S W L S L C ox C ox /S I d S I d

4 Current Velocity Saturation Current V DSAT Lν sat µ n I DS ν sat C OX W V GS V T V DSAT V gs= V S V 2 V TH S V TH L S L V DSAT S V DSAT W S W C ox C ox /S I d S I d 19 Gate Delay τ gd =Q/I=(CV)/I V S V I d S I d τ gd S τ gd Gate Delay 20 Overall Scaling Results, Transistor Speed and Leakage. Preliminary Data from 2005 ITRS. HP = High-Performance Logic LOP = Low Operating Power Logic LSTP = Low Standby Power Logic Intrinsic Transistor Delay, τ = CV/I (lower delay = higher speed) Leakage Current (HP: standby power dissipation issues) ITRS 2009 Transistor Speed LOP LSTP HP LOP HP Target: 17%/yr, historical rate 17%/yr rate 21 Planar Bulk MOSFETs LSTP Target: Isd,leak ~ 10 pa/um Advanced MOSFETs RO=Ring Oscillator 22 Wire Delay Power Dissipation (Dynamic) Wire delay τ wire =R C assuming (logical) wire lengths remain constant... Capacitive (Dis)charging P=(1/2)CV 2 f Increase Frequency? τ gd S τ gd R R/S τ wire τ wire Important cost shift we will have to watch 23 V S V P S 3 P So: f f/s? P S 2 P 24 4

5 Effects? Power Density Area S 2 Capacitance S Resistance 1/S Threshold (V th ) S Current (I d ) S Gate Delay (τ gd ) S Wire Delay (τ wire ) 1 Power S 2 S 3 25 P S 2 P (increase frequency) P S 3 P (dynamic, same freq.) A S 2 A Power Density: P/A two cases? P/A P/A increase freq. P/A S P/A same freq. 26 Cheating Improving Resistance Don t like some of the implications High resistance wires Higher capacitance Atomic-scale dimensions. Quantum tunneling Need for more wiring Not scale speed fast enough 27 R=ρL/(W t) W S W L, t similar R R/S What might we do? Don t scale t quite as fast now taller than wide. Decrease ρ (copper) introduced Capacitance and Leakage Capacitance per unit area C ox = ε SiO 2 /T ox T ox S T ox C ox C ox /S What s wrong with Tox = 1.2nm? 29 source: Borkar/Micro

6 Capacitance and Leakage Capacitance per unit area C ox = ε SiO 2 /T ox T ox S T ox C ox C ox /S What might we do? Reduce Dielectric Constant ε (interconnect) and Increase Dielectric to substitute for scaling T ox (gate quantum tunneling) 31 Table PIDS3B Low Operating Power Technology Requirements ITRS 2009 Grey cells delineate one of two time periods: either before initial production ramp has started for ultra-thin body fully depleted (UTB FD) SOI or multi-gate (MG) MOSFETs, or beyond when planar bulk or UTB FD MOSFETs have reached the limits of practical scaling (see the text and the table notes for further discussion). Year of Production MPU/ASIC Metal 1 (M1) ½ Pitch (nm) (contacted) Lg: Physical Lgate for High Performance logic (nm) L g: Physical Lgate for Low OperatingPower (LOP) logic (nm) [1] EOT: Equivalent Oxide Thickness (nm) [2] Extended planar bulk UTB FD MG Gate poly depletion (nm) [3] Bulk Channel doping (E18 /cm3) [4] Extended Planar Bulk Junction depth or body Thickness (nm) [5] Extended Planar Bulk (junction) UTB FD (body) MG (body) EOT elec: Electrical Equivalent Oxide Thickness (nm) [6] Extended Planar Bulk UTB FD MG High-K dielectric Survey Intel NYT Announcement Intel Says Chips Will Run Faster, Using Less Power NYT 1/27/07, John Markov Claim: most significant change in the materials used to manufacture silicon chips since Intel pioneered the modern integratedcircuit transistor more than four decades ago Intel s advance was in part in finding a new insulator composed of an alloy of hafnium will replace the use of silicon dioxide. Wong/IBM J. of R&D, V46N2/3P , Wire Layers = More Wiring Typical chip cross-section illustrating hierarchical scaling methodology [ITRS2005 Interconnect Chapter] 6

7 Improving Gate Delay τ gd =Q/I=(CV)/I V S V I d =(µc OX /2)(W/L)(V gs -V TH ) 2 I d S I d τ gd S τ gd Lower C. Don t scale V. How might we accelerate? Don t scale V: V V I I/S τ gd S 2 τ gd 37 But Power Dissipation (Dynamic) Capacitive (Dis)charging P=(1/2)CV 2 f V V Increase Frequency? f f/s 2? P P/S If not scale V, power dissipation not scale down. 38 And Power Density Historical Voltage Scaling P P/S (increase frequency) But Α S 2 Α What happens to power density? P/A (1/S 3 )P Power Density Increases this is where some companies have gotten into trouble 39 Frequency impact? Power Density impact? 40 Scale V separately from S Power Density Impact τ gd =Q/I=(CV)/I V I d =(µc OX /2)(W/L)(V gs -V TH ) 2 I d V 2 /S I d τ gd (SV/(V 2 /S)) τ gd τ gd (S 2 /V) τ gd Ideal scale: S=1/100 V=1/100 τ=1/100 F ideal =100 Cheating: S=1/100 V=1/10 τ=1/1000 F cheat =1000 f cheat /f ideal =10 41 P=1/2CV 2 f P~= S V 2 (V/S 2 ) = V 3 /S P/A = (V 3 /S) / S 2 = V 3 /S 3 V=1/10 S=1/100 P/A 1000 (P/A) 42 7

8 uproc Clock Frequency up Power Density MHz Watts The Future of Computing Performance: Game Over or Next Level? National Academy Press, The Future of Computing Performance: Game Over or Next Level? National Academy Press, The Red Brick Wall ITRS vs 1999 Red Brick = ITRS Technology Requirement with no known solution Alternate definition: Red Brick = something that REQUIRES billions of dollars in R&D investment [from Andrew Kahng] 45 Source: Semiconductor International - [from Andrew Kahng] 46 ITRS 2009 Year of Production MPU/ASIC Metal 1 (M1) ½ Pitch (nm) (contacted) Lg: Physical Lgate for High Performance logic (nm) L g: Physical Lgate for Low OperatingPower (LOP) logic (nm) [1] EOT: Equivalent Oxide Thickness (nm) [2] Extended planar bulk UTB FD MG Gate poly depletion (nm) [3] Bulk Channel doping (E18 /cm3) [4] Extended Planar Bulk Junction depth or body Thickness (nm) [5] Extended Planar Bulk (junction) UTB FD (body) MG (body) EOT elec: Electrical Equivalent Oxide Thickness (nm) [6] Extended Planar Bulk UTB FD MG C g ideal (ff/µm) [7] Extended Planar Bulk UTB FD MG J g,limit: Maximum gate leakage current density (A/cm 2 ) [8] Extended Planar Bulk UTB FD MG V dd: Power Supply Voltage (V) [9] Bulk/UTB FD/MG V t,sat: Saturation Threshold Voltage (mv) [10] Extended Planar Bulk UTB FD MG I sd,leak (na/µm) [11] Bulk/UTB FD/MG Mobility enhancement factor due to strain [12] Bulk/UTB FD/MG Effective Ballistic Enhancement Factor, Kbal [13] Bulk/UTB FD/MG R sd: Effective Parasitic series source/drain resistance (Ω-µm) [14] Extended Planar Bulk UTB FD MG I d,sat: NMOS Drive Current with series resistance (µa/µm) [15] Extended Planar Bulk UTB FD ,080 1,050 MG 1,070 1,120 1,100 1,190 1,130 1,210 1,140 1,200 1,320 1,370 C g fringing capacitance (ff/µm) [16] Extended Planar Bulk UTB FD MG C g,total: Total gate capacitance for calculation of CV/I (ff/µm) [17] Extended Planar Bulk UTB FD MG τ =CV/I: NMOSFET intrinsic delay (ps) [18] 47 Extended Planar Bulk UTB FD MG Conventional Scaling Ends in your lifetime Perhaps already: "Basically, this is the end of scaling. May 2005, Bernard Meyerson, V.P. and chief technologist for IBM's systems and technology group 48 8

9 HW5 Regions Admin Hardest yet hope you ve started Due Tuesday Big Ideas [MSB Ideas] Moderately predictable VLSI Scaling unprecedented capacities/capability growth for engineered systems change be prepared to exploit account for in comparing across time but not for much longer