1 Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed out ECE 1192, 2006, Steven Levitan, University of Pittsburgh
2 Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models for SPICE simulation Analysis of secondary and deep-submicron effects Future trends
3 The DIODE B Al A SiO 2 p n Cross-section of pn-junction in an IC process A p n B One-dimensional representation Al A B diode symbol Mostly occurring as parasitic element in Digital ICs
4 Diodes in a CMOS circuit Copyright 2005 Pearson Addison-Wesley. All rights reserved.
5 Depletion Region Formation hole diffusion electron diffusion p n (a) Current flow. hole drift electron drift Charge Density - ρ + x Distance (b) Charge density. Electrical Field ξ x (c) Electric field. Potential V ψ 0 -W 1 W 2 x (d) Electrostatic potential.
6 Formation and characteristics of a pn junction Digital Integrated Circuits 2nd Introduction to Circuits, Fourth Edition by Peter Uyemura, Devices Copyright 2004 John Wiley & Sons. All rights reserved.
7 Forward Bias p n (W 2 ) p n0 L p n p0 p-region -W 1 0 W 2 n-region x diffusion Typically avoided in Digital ICs
8 Reverse Bias p n0 n p0 p-region -W 1 0 W 2 n-region x diffusion The Dominant Operation Mode
9 Diode Current a Simple Model
10 Models for Manual Analysis V D + I D = I S (e V D/φT 1) V D + + I D V Don (a) Ideal diode model (b) First-order diode model
11 PN Junction Diode DC Model (Details) Thermal Voltage Ф T = kt/q V ( 300 K) k Boltzmann constant ( x10-23 J/K) T Absolute temperature ( K) q Electron charge ( x10-19 C) I s In practice, this term has to be obtained by characterization since it is highly dependent on doping concentration, dimension, operative temperature etc. ECE , Steven Levitan, University of Pittsburgh
12 PN Junction: Dynamic Effects Primary effects Junction Capacitance Diffusion Capacitance Secondary Effects Avalanche Breakdown ECE , Steven Levitan, University of Pittsburgh
13 Junction Capacitance
14 Diffusion Capacitance
15 Integrated Diode Model R S + V D - I D C D
16 SPICE Parameters
17 The MOS Transistor Polysilicon Aluminum
18 Controlling current flow in an nfet. Digital Integrated Circuits 2nd Introduction to Circuits, Fourth Edition by Peter Uyemura, Devices Copyright 2004 John Wiley & Sons. All rights reserved.
19 Controlling current flow in an pfet. Digital Integrated Circuits 2nd Introduction to Circuits, Fourth Edition by Peter Uyemura, Devices Copyright 2004 John Wiley & Sons. All rights reserved.
20 What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D
21 MOS Transistors - Types and Symbols D D G G S NMOS Enhancement D S NMOS Depletion D G G B PMOS Enhancement S S NMOS with Bulk Contact
22 MOS Transistors Regions Transitions Copyright 2005 Pearson Addison-Wesley. All rights reserved.
23 MOS Transistors Operating regions Copyright 2005 Pearson Addison-Wesley. All rights reserved.
24 Threshold Voltage: Concept S - V GS + G D n+ n+ n-channel p-substrate Depletion Region B
25 Threshold Voltage - Derivation
26 The Body Effect input NAND gate V DD 0.75 V T (V) V (V) BS B A N2 N1 Drain of N1 is Source of N2 VSB of N2 >= 0
27 Current-Voltage Relations A good ol transistor -4 x 10 6 VGS= 2.5 V 5 4 Resistive Saturation VGS= 2.0 V I D (A) 3 V DS = V GS -V T Quadratic Relationship 2 VGS= 1.5 V 1 VGS= 1.0 V V DS (V)
28 Transistor in Linear S V GS G V DS D I D n + V(x) + n + L x p-substrate B MOS transistor and its bias conditions
29 Transistor in Saturation V GS G V DS > V GS - V T S D n+ - V GS - V T + n+ Pinch-off
30 Current-Voltage Relations Long-Channel Device Cut-off (V GS V T < 0) no current (not really)
31 Current-Voltage Relations The Deep-Submicron Era 2.5 x Early Saturation VGS= 2.5 V 1.5 VGS= 2.0 V I D (A) 1 VGS= 1.5 V Linear Relationship 0.5 VGS= 1.0 V V DS (V)
32 Velocity Saturation υ n (m/s) υ sat = 10 5 Constant velocity Constant mobility (slope = µ) ξ c = 1.5 ξ (V/µm)
33 Perspective I D Long-channel device V GS = V DD Short-channel device V DSAT V GS -V T V DS
34 I D versus V GS 6 x x quadratic linear I D (A) 3 I D (A) V GS (V) Long Channel 0.5 quadratic V GS (V) Short Channel
35 I D versus V DS I D (A) 6 x VGS= 2.5 V Resistive Saturation VGS= 2.0 V V DS = V GS -V T VGS= 1.5 V I D (A) x 10 VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V 1 VGS= 1.0 V 0.5 VGS= 1.0 V V DS (V) Long Channel V DS (V) Short Channel
36 A unified model for manual analysis G S D B
37 Simple Model versus SPICE 2.5 x 10-4 V DS =V DSAT Velocity Saturated I D (A) 1 Linear 0.5 V DSAT =V GT V DS =V GT Saturated V DS (V)
38 A PMOS Transistor 0 x 10-4 VGS = -1.0V -0.2 VGS = -1.5V -0.4 I D (A) -0.6 VGS = -2.0V Assume all variables negative! -0.8 VGS = -2.5V V DS (V)
39 Transistor Model for Manual Analysis
40 The Transistor as a Switch V GS V T S Ron I D D V GS = V DD R mid R 0 V DD /2 V DD V DS
41 The Transistor as a Switch 7 x R eq (Ohm) V DD (V)
42 The Transistor as a Switch
43 MOS Capacitances Dynamic Behavior
44 Dynamic Behavior of MOS Transistor G C GS C GD S D C SB C GB C DB B
45 Physical visualization of FET capacitances Digital Integrated Circuits 2nd Introduction to Circuits, Fourth Edition by Peter Uyemura, Devices Copyright 2004 John Wiley & Sons. All rights reserved.
46 MOS Capacitances Behavior! Copyright 2005 Pearson Addison-Wesley. All rights reserved.
47 The Gate Capacitance in an n-channel n MOSFET Digital Integrated Circuits 2nd Introduction to Circuits, Fourth Edition by Peter Uyemura, Devices Copyright 2004 John Wiley & Sons. All rights reserved.
48 The Gate Capacitance Polysilicon gate Source n + x d x d W Drain n + L d Top view Gate-bulk overlap t ox Gate oxide n + L n + Cross section
49 Gate Capacitance Copyright 2005 Pearson Addison-Wesley. All rights reserved.
50 Gate Capacitance Behavior G G G S C GC C GC C GC D S D S D Cut-off Resistive Saturation Most important regions in digital design: saturation and cut-off
51 Gate Capacitance Behavior WLC ox C GC WLC ox C GC 2WLC ox WLC ox 2 C GC B C GCS = C GCD WLC ox 2 C GCS C GCD 3 V GS 0 V DS /(V GS -V T ) 1 Capacitance as a function of VGS (with VDS = 0) Capacitance as a function of the degree of saturation
52 Measuring the Gate Cap I V GS Gate Capacitance (F) V GS (V)
53 Diffusion Capacitance Channel-stop implant N A 1 Side wall W Source N D Bottom x j L S Side wall Substrate N A Channel
54 Junction capacitances in a MOSFET Digital Integrated Circuits 2nd Introduction to Circuits, Fourth Edition by Peter Uyemura, Devices Copyright 2004 John Wiley & Sons. All rights reserved.
55 Calculation of the FET junction capacitance Digital Integrated Circuits 2nd Introduction to Circuits, Fourth Edition by Peter Uyemura, Devices Copyright 2004 John Wiley & Sons. All rights reserved.
56 Junction capacitance variation with reverse voltage Digital Integrated Circuits 2nd Introduction to Circuits, Fourth Edition by Peter Uyemura, Devices Copyright 2004 John Wiley & Sons. All rights reserved.
57 Final construction of the nfet RC model C G Digital Integrated Circuits 2nd Introduction to Circuits, Fourth Edition by Peter Uyemura, Devices Copyright 2004 John Wiley & Sons. All rights reserved.
58 Capacitances in 0.25 μm m CMOS process Values for a Typical Device:
59 The Sub-Micron MOS Transistor Threshold Variations Sub-threshold Conduction Parasitic Resistances
60 Threshold Variations V T V T Long-channel threshold Low V DS threshold Threshold as a function of the length (for low V DS ) L V DS Drain-induced barrier lowering (for low L)
61 Sub-Threshold I D vs VGS qvgs nkt I D I0e 1 e qv = kt DS Log Scale V DS from 0 to 0.5V
62 Sub-Threshold I D vs VDS I D qvgs qv = nkt kt I e 0 1 e DS ( 1+ λ V ) DS V GS from 0 to 0.3V Linear scale
63 Summary of MOSFET Operating Regions Strong Inversion V GS >V T Linear (Resistive) V DS <V DSAT Saturated (Constant Current) V DS V DSAT Weak Inversion (Sub-Threshold) V GS V T Exponential in V GS with linear V DS dependence
64 Parasitic Resistances G Polysilicon gate L D Drain contact V GS,eff S D W R S R D Drain
65 Latchup V DD V DD p + n + n + p + p + n + R nwell p-source n-well R nwell R psubs p-substrate n-source R psubs (a) Origin of latchup (b) Equivalent circuit
66 SPICE MODELS Level 1: Long Channel Equations - Very Simple Level 2: Physical Model - Includes Velocity Saturation and Threshold Variations Level 3: Semi-Emperical - Based on curve fitting to measured devices Level 4 (BSIM): Emperical - Simple and Popular
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan firstname.lastname@example.org TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
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