# LECTURE 3 MOSFETS II. MOS SCALING What is Scaling?

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1 LECTURE 3 MOSFETS II Lecture 3 Goals* * Understand constant field and constant voltage scaling and their effects. Understand small geometry effects for MOS transistors and their implications modeling and scaling. Understand and model the capacitances of the MOSFET as: ) lumped, voltage-dependent capacitances, 2) lumped, fixed-value capacitances, and Be able to calculate these capacitances from basic parameters. Assignment Kang and Leblebici: pp. 8-0 *Lecture length - 20 minutes /7/98 3/3/0 MOS SCALING What is Scaling? Reduction in size of an MOS chip by reducing the dimensions of MOSFETs and interconnects. Reduction is systematic and preserves geometric ratios important to the functioning of the chip. Ideally, allows design reuse. Assume that S is the scaling factor. Then a transistor with original dimensions of L and W becomes a transistor with dimensions L/S and W/S. Typical values of S:.4 to.5 per biennium. 5.0 µ in 980 to 0.25 µ in 998 to 0.8 µ in Two major forms of scaling: Full scaling (constant-field scaling) All dimensions are scaled by S and the supply voltage and other voltages are also scaled. Constant-voltage scaling The voltages are not scaled and, in some cases, dimensions associated with voltage are not scaled. 2 /7/98 3/3/0

2 MOS SCALING What happens to a MOSFET during scaling? Parameter Before Scaling After Full Scaling After Constant Voltage Scaling Channel length L L/S L/S Channel width W W/S W/S Gate oxide thickness t ox t ox /S t ox /S* Junction Depth x j x j /S x j /S Doping Densities N A, N D S N A, S N D S 2 N A, S 2 N D Power supply voltage V DD V DD /S V DD Threshold Voltage V T0 V T0 /S V T0 * In some forms of constant voltage scaling t ox 3 /7/98 3/3/0 MOSFET SCALING How is Doping Density Scaled? Parameters affected by substrate doping density: ) the depths of the source and drain depletion regions, 2) possibly the depth of the channel depletion region and 3) possibly V T. Channel depletion region and V T are not good candidates for deriving general relationships since channel implants are used to tune V T. Thus, we focus our argument depletion region depth of the source and drain which is given by: 2 ε Si N A + N D x d = φ q N A N 0 V D in which: φ 0 = kt ln q N A N D n i 4 /7/98 3/3/0

3 MOS SCALING How is Doping Density Scaled?(Continued) Assuming N A small compared to N D and φ 0 small compared to V (the reverse bias voltage which ranges from 0 to V DD ), x d V N A in which represents proportional to. Assuming constant voltage scaling with scaling factor S, x d scales as follows: -- x S d Thus, for constant voltage scaling, N A => S 2 N A. -- S V N A = S 2 V NA 5 /7/98 3/3/0 MOS SCALING How is Doping Density Scaled?(Continued) On the other hand, for full scaling, V => V/S giving: -- x S d -- S V N A = S 2 V NA = S V N --- A S Thus, for full scaling, N A => S N A 6 /7/98 3/3/0

4 MOS SCALING Which Type of Scaling Behaves Best? Constant Voltage Scaling 7 /7/98 3/3/0 Practical, since the power supply and signal voltages are unchanged But, I D C ox W/L V 2 and C ox /t ox. So, I D => S I D. W => W/S and x j => x j /S for the source and drain (same for metal width and thickness), so J D => S 3 J D, increasing current density by S 3. Causes self-heating and metal migration in interconnects. Since V => V and I D => S I D, the power P => S P. Since for area A, A => A/S 2, the power density per unit area increases by factor S 3. Causes localized heating and heat dissipation problems. Electric field increases by factor S. Can cause failures such as oxide breakdown, punch-through, and hot electron charging of the oxide (discussed next). With all of these problems, why not use full scaling reducing voltages as well? Over last several years, departure from 5.0 V supplies: 3.3 V, 2.5 V,... Other Types of Scaling? Does Scaling Really Work? Not totally as dimension become small, giving us our next topic. SMALL GEOMETRY EFFECTS Short-Channel Effects General Due to small dimensions: Effects always present, but masked for larger channel lengths Effects absent until a channel dimension becomes small Many, but not all of these effects represented in SPICE, so a number of the derivations or results influence SPICE device models. Short-Channel Effects What is a short-channel device? Channel length of the same order of magnitude as ) depletion region thicknesses of source and drain junctions or 2) effective channel length approximately equal to the source and drain junction depth. Velocity Saturation and Surface Mobility Degradation Drift velocity v d for channel electrons is proportional to electric field along channel For electric fields along the channel of 0 5 V/cm (as occur as L 8 /7/98 3/3/0

5 SMALL GEOMETRY EFFECTS Short Channel Effects becomes small with V DD fixed), v d saturates and becomes a constant v d(sat) = 0 7 cm/s. This reduces I D which no longer depends quadratically on V GS. Vertical field effects cause µ n to decline represented by effective surface mobility µ n(eff). Empirical formulas for µ n(eff) on p. 87 and 88 of Kang and Leblebici use parameters Θ and η. 9 /7/98 3/3/0 Channel Depletion Region Charge Reduction Often viewed as the short channel effect At the source and drain ends of the channel, channel depletion region charge is actually depletion charge for the source and drain For L large, attributing this charge to the channel results in small errors But for short-channel devices, the proportion of the depletion charge tied to the source and drain becomes large Mathematical representation of this phenomena is based on geometric arguments given in Kang and Leblebici Fig SMALL GEOMETRY EFFECTS Short Channel Effects The reduction in charge is represented by the change of the channel depletion region cross-section from a rectangle of length L and depth x dm to a trapezoid with lengths L and L L S L D and depth x dm. This trapezoid is equivalent to a rectangle with length: L S + L D L L Thus, the channel charge per unit area is reduced by the factor: L S + L D L Next, need L S and L D in terms of the source and drain junction depths and depletion region junction depth using more geometric arguments. Once this is done, the resulting reduction in threshold voltage V T due to the short channel effect can be written as: 0 /7/98 3/3/0

6 SMALL GEOMETRY EFFECTS Narrow Channel Effect V T0 = x j qε C Si N A 2φ F ox 2L 2x ds x j + + in which x j junction depth of source and drain x ds Depth of the source depletion region x dd Depth of the drain depletion region See plot in Kang and Leblebici - p. 92. For 5 µ, effect is negligible. But at 0.5 µ, V T0 reduced to 0.43 from 0.76 volts ( V T0 = 0.33 V). Narrow-Channel Effect 2x dd x j The channel depletion region spreads out under the polysilicon as it rises over the thick oxide. See Kang and Leblebici Fig Thus, there is extra charge in the depletion region. The increase in V T due to this extra charge: /7/98 3/3/0 SMALL GEOMETRY EFFECTS Subthreshold Conduction κ x dm V T0 = C qε Si N A 2φ F W ox in which κ is an empirical parameter dependent upon the assumed added charge cross-section. Note that this as added to V T0 and hence may offset much of the short channel effect which is subtracted from V T0. Subthreshold Conduction The potential barrier that prevents channel formation is actually controlled by both the gate voltage V GS and the drain voltage V DS. V DS lowers this potential, an effect known as DIBL (Drain-Induced Barrier Lowering). If the barrier is lowered sufficiently by V GS and V DS, then there is channel formation for V GS < V T0. Subthreshold current is the result. Upward curvature of the I D versus V GS curve for V GS < V T with V DS 0. 2 /7/98 3/3/0

7 SMALL GEOMETRY EFFECTS Other Effects Punch-Through Merging of depletion region of the source and drain Carriers injected by the source into the depletion region are swept by the strong field to the drain. With the deep depletion, a large current under limited control of V GS and V SB results. Thus, normal operation of devices in punch-through not feasible. Limits small device size and allowed power supply voltage. Thinning of t ox As oxide become thin, pinholes in the oxide can occur. Can cause electrical shorts between the gate and substrate. Also, dielectric strength of the thin oxide may permit oxide breakdown due to application of an electric field in excess of breakdown field. May cause permanent damage due to current flow through the oxide. 3 /7/98 3/3/0 SMALL GEOMETRY EFFECTS Other Effects Hot Electron Effects High electric fields in both the channel and pinch-off regions for short channel lengths occur for small L. Particularly apparent in the pinch-off region where voltage V DS V D(sat) large with L L eff small causes very high fields. High electric fields accelerate electrons which have sufficient energy with the accompanying vertical field to be injected into the oxide and are trapped in defect sites or contribute to interface states. These are called hot electrons. See Kang and Leblebici Fig Resulting trapped charge increases V T and otherwise affects transconductance, reducing the drain current. Since these effects are concentrated at the drain end of the channel, the effects produce asymmetry in the I-V characteristics seen in Kang and Leblebici Fig Effect further aggravated by impact ionization. 4 /7/98 3/3/0

8 SMALL GEOMETRY EFFECTS Other Effects An Attack on Punch-through and Hot Electron Effects To deal with these limitations on size, device designers use changes in device geometry. Notable among these is the lightly-doped drain (LDD) (note symmetry): Normal Drain: V LDD: V L V = V P + V L Source V P Drain Shallower Drains and Depletion Regions What about modeling LDDs? Not done in typical SPICE models. Need for use of more complex models derived by 3-D device simulation. HSPICE model available. 5 /7/98 3/3/0 TRANSISTOR DIMENSIONS In layout, use drawn dimensions in calculations, use effective (actual) dimensions Definition of notation varies widely. L and W are drawn dimensions in some cases and effective dimensions in others. Carefully define the situation in terms of drawn (drn) and effective (eff) dimensions using StarSpice notation. Where L and W used, must know which is meant in the specific case. HSpice Notation: L poly = L drn + XL actual poly width after etching L eff = L poly 2 LD = L drn + XL 2 LD effective (actual) channel length W = W drn + XW width of field oxide opening W eff = W 2 WD effective (actual) channel length where WD is lateral diffusion of channel stop. 6 /7/98 3/3/0

9 TRANSISTOR DIMENSIONS (Continued) Looking at top view of layout and actual transistor: Y drn Polysilicon L drn XW/2 + WD W drn Diffusion Channel W eff Diffusion Layout L eff XL/2 L D Other parameters used: L reduction in channel length; L eff = Ldrn L W reduction in channel width; W eff = Wdrn W In terms of the StarHSpice parameters: L = XL + 2 LD or L = XL + 2 dl W = XW + 2WD or W = XW + 2dW dl = LINT + LL/L LLN + LW/W LWN + LWL/(L LLN W LWN ) 7 /7/98 3/3/0 TRANSISTOR DIMENSIONS (Continued) LL, LW, and LWL default to 0, leaving LINT. LINT - Length offset fitting parameter from I-V at 0 bias. Similar equation for dw. Assumptions we use:. Manual Calculations: Find L eff and W eff using all available length and width change parameters unless stated otherwise. Use L = L eff and W = W eff in equations. 2. Level 3 Spice/HSPice Models: a) If L given and LD not in model, L = L eff = L drn L b) else if L given and LD in model, L = L poly = L drn L + 2 LD. c) else if no L given and LD not in model, L = L eff = L drn 2 LD; d) else if no L given and LD in model, L = L drn. e) W = W eff = W drn W 3. Level 4 Spice/Level XX HSpice Models: L = L drn and W = W drn, assume all variations taken into account in model. 8 /7/98 3/3/0

10 Oxide Capacitances Parameters studied so far apply to steady-state (DC) behavior. We now add parameters modeling transient behavior. MOSFET capacitances are distributed and complex. But, for tractable modeling, we use lumped approximations. Two categories of capacitances: ) oxide-related and 2) junction. Inter-terminal capacitances result as follows: G C gs C gd S DC Model C gb D C db C sb B 9 /7/98 3/3/0 Overlap Capacitances Capacitances C gx where x is b, s, or d Have the thin oxide as their dielectric Overlap Capacitances Two special components of C gs and C gd caused by the lateral diffusion under the gate and thin oxide Length of each is lateral diffusion length L D Width is W, the channel width of the channel Capacitance per unit area is C ox = ε ox /t ox. Thus, and C GS(overlap) = C ox W L D C GD(overlap) = C ox W L D model the overlap. These capacitances are an added component of C gs and C gd. 20 /7/98 3/3/0

11 Gate-to-Channel Charge Capacitances Remaining oxide capacitances not fixed, but are dependent on the mode of operation of the transistor; referred to as being bias-dependent. Capacitances between the gate and the source and the gate and the drain are really distributed capacitances between the gate and the channel apportioned to the source and drain. Cutoff No channel formation => C gs = C ds = 0. The gate capacitance to the substrate Linear C gb = C ox W L The channel has formed and the capacitance is from the gate to the source and drain, not to the substrate. Thus, C gb = 0 and 2 /7/98 3/3/0 Gate-to-Channel Charge Capacitances Saturation C gs C -- C ds 2 ox W L In saturation, the channel does not extend to the drain. Thus, C gd = 0 and 2 C gs -- C 3 ox W L These capacitances as a function of V GS (and V DS ) can be plotted as in Kang and Leblebici Fig Note the changes in capacitance in the three operating modes. Also note that the capacitance seen looking into the gate is C g : 2 -- C 3 ox W L C g = C gb + C gs + C gd C ox W L For manual calculations, we approximate C g as its maximum value. See Kang & Leblebici Table 3.6 and Figure /7/98 3/3/0

12 Junction Capacitances Note that this important input capacitance is directly proportional to L and W and inversely proportional to t ox. These relationships will be important in our designs. Junction Capacitances Capacitances associated with the source and the drain Capacitances of the reversed biased substrate-to-source and substrate-to-drain p-n junctions. Lumped, but if the diffusion used as a conductor of any length, both its capacitance and resistance need to be modeled in a way that tends more toward a distributed model which is used for resistive interconnect. 23 /7/98 3/3/0 Junction Capacitance Geometry The Geometry G Y x j D W Junction between p substrate and n+ drain (Bottom) Area: W ( Y + x j ) = AD Junction between p+ channel stop and n+ drain ( Sidewalls ) Area: x j ( W + 2 Y ) = x j PD 24 /7/98 3/3/0

13 Junction Capacitance Geometry (Continued) Since the diffusion also enters into contacts at a minimum here, actual geometries will be more complex, but the fundamental principles remain: Why separate bottom and sides? The carrier concentration in the channel stop areas is an order of magnitude higher (~ 0 N A ) than in the substrate (N A ). This results in a higher capacitance for the sidewalls. The bottom and channel edge can be treated together via AD in the SPICE model but often channel edge either ignored or included in PD. All other areas are treated together via the length of the perimeter PD in the SPICE model. The capacitance in this case is per meter since dimension x j is incorporated in the capacitance value. Same approach for source. 25 /7/98 3/3/0 Junction Capacitances/Unit Area Two junction capacitances per unit are for each distinct diffusion region, the bottom capacitance and the sidewall capacitance. Equations are the same, but values different. Thus, we use a single value C j which is the capacitance of a p-n junction diode. Recall that most of the depletion region in a diode lies in the region with the lower impurity concentration, in this case, the p-type substrate. Finding the depletion region thickness in term of basic physical parameters and V the applied voltage (note that V is negative since the junction is reversed biased). The junction potential in this equation is: 2 ε Si N A + N D x d = ( φ q N A N 0 V) D 26 /7/98 3/3/0

14 Junction Capacitances/Unit Area (Continued) φ 0 = kt q N A N D ln n i The total depletion region charge can be calculated by using x d : N A N D N A N D Q j = A q x N A + N D d = A 2 ε Si q ( φ N A + N D 0 V) The capacitance found by differentiating Q j with respect to V to give: C j ( V) dq = j = dv A C j V φ 0 with: ε Si q N A N D C j0 = N A + N D φ 0 27 /7/98 3/3/0 Junction Capacitances Approximations This derivation for an abrupt junction. For a graded junction, the power /2 in the denominator of C j (V) is replaced by grading coefficient m (/3 for a linearly graded junction). Approximation for Manual Calculations The voltage dependence of C j (V) makes manual calculations difficult. An equivalent capacitance for a voltage change from V to V2 in the reverse bias is derived in the book with the final version: C eq = A C j0 K eq with voltage equivalence factor K eq (0 < K eq < ), 2 φ 0 K eq = ( φ V 2 V 0 V 2 φ 0 V ) 28 /7/98 3/3/0

15 SUMMARY Full scaling (constant field scaling) better than constant voltage scaling if the power supply value can be changed. Scaling is subject to small geometry effects that create new limitations and require new modeling approaches. The short-channel effect, narrow-width effect, mobility degradation, and subthreshold conduction all bring new complications to the modeling of the MOSFET. Geometric and capacitance relationships developed permit us to calculate: the two overlap capacitances due to lateral diffusion, the three transistor-mode dependent oxide capacitances, the voltage-dependent bottom and sidewall junction capacitances for the source and drain, and fixed capacitance source and drain capacitance values for a voltage transition in manual calculations. 29 /7/98 3/3/0

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