EE 560 MOS TRANSISTOR THEORY
|
|
- Iris Carr
- 6 years ago
- Views:
Transcription
1 1 EE 560 MOS TRANSISTOR THEORY PART 1
2 TWO TERMINAL MOS STRUCTURE V G (GATE VOLTAGE) 2 GATE OXIDE SiO 2 SUBSTRATE p-type doped Si (N A = to cm -3 ) t ox V B (SUBSTRATE VOLTAGE) EQUILIBRIUM: n p = n 2 i (n i 1.45 x cm -3 ) Let SUBSTRATE be uniformy N A 2 n p0 n i and p N p0 = N A A (BULK concentrations)
3 ENERGY BAND DIAGRAM FOR p - TYPE SUBSTRATE 3 qχ = electron affinity of Si φ F = E F E i q Work Function qφ S = q χ + (E c E F ) φ Fp = kt (N A >> n i ) (N D >> n i ) q ln n i φ F n = kt N A q ln N D n i n i = 1.45 x cm room temp, k = 1.38 x J/ o K, => kt/q = 26 room temp q = 1.6 x C
4 ENERGY BAND DIAGRAMS FOR COMPONENTS OF MOS STRUCTURE 4 E o E Fm METAL (Al) qφ M = qχ m = 4.1 ev Ec OXIDE SEMICONDUCTOR (Si) qχ ox = 0.95 ev qφ S qχ Si = 4.15 ev E c band-gap: E g = 8 ev E Fp E i band-gap: E g = 1.1 ev qφ Fp E v E v Φ S > Φ M => p-type Si Φ M > Φ S => n-type Si
5 Equilibrium V G = 0 5 Oxide p-type Si Substrate Flat-band voltage: V FB = Φ M - Φ S volts Built-in potential: V B = 0 Equilibrium E c qφ M qφ S E Fm φ s = surface potential qφ s qφ F E Fp E v E i METAL (Al) OXIDE SEMICONDUCTOR (Si)
6 MOS SYSTEM WITH EXTERNAL BIAS Accumulation Region V G < 0 7 E OX E OX Oxide p-type Si Substrate holes ACCUMULATED on the Si surface V B = 0 V G = 0 Equilibrium Oxide p-type Si Substrate V B = 0
7 Depletion Region MOS SYSTEM WITH EXTERNAL BIAS V G > 0 (small) 8 E OX E OX Oxide p-type Si Substrate DEPLETION Region V B = 0 E c E Fm qv G E i E Fp E v METAL (Al) OXIDE SEMICONDUCTOR (Si)
8 MOS SYSTEM BIASED IN DEPLETION REGION 9 V G > 0 (small) 0 x d x x d E OX E OX Oxide p-type Si Substrate DEPLETION Region V B = 0 Mobile charge in thin layer parallel to Si surface Change in surface potential to displace dq Depletion Region Charge
9 Inversion Region MOS SYSTEM WITH EXTERNAL BIAS V G > 0 (large) 10 x dm E OX E OX Oxide p-type Si Substrate Electrons attracted to Si surface Inversion Condition φ s = -φ F V B = 0 x dm = x d φ s = φf = 2ε Si 2φ F qn A E c E Fm qv G φ s = -φ F E i E Fp E v METAL (Al) OXIDE SEMICONDUCTOR (Si)
10 G G G G G G 11 D S D S B B n-channel enhancement S B DS B D S D B p-channel enhancement B S I DS DS -V Tp I DS DS 0 V GS GS 0 +V Tn Tn V GS GS n-channel depletion G I DS DS D S I DS DS 0 +V Tp +V Tp p-channel depletion V GS GS B -V Tn Tn 0 V GS GS
11 B S G W D 12 L oxide n + n + substrate or bulk B p conducting channel depletion layer N-CHANNEL ENHANCEMENT-TYPE MOSFET nmos Layout polysilicon gate L W active area metal contact area
12 B S G D D G S B 13 p+ p+ n+ n+ n-well p -substrate V GS < V Tn CUT-OFF REGION 0 < V GS < V Tn DEPLETION REGION V GS V DS B ( G 2 ) S n + C GC GC CC BC BC G oxide D n + n + depletion region depletion region substrate or or bulk bulk B B p p
13 V GS > V Tn INVERSION REGION 14 V GS VDS B ( G 2 ) S n + C GC GC C C BC BC G oxide D n + n + n + substrate or or bulk B p conducting channel or inversion region depletion region Underneath Gate V G = V Tn E c E Fm qv Tn 2φ F -φ F φ F E i E Fp E v METAL (Al) OXIDE SEMICONDUCTOR (Si)
14 MOS Capacitance t ox = 50 nm, ε ox = 0.34 pf/cm => = 6.8 x 10-8 F/cm 2 W x L = 50 µm x 50 µm => C GC = 170 ff Depletion Capacitance C j = ε Si C BC = WLC j, x d φ Fp = kt q ln n i N A N A = 3 x cm -3, n i = 1.45 x cm -3 => φ F = V (recall that at room temp or 27 o C kt/q = 26 mv) C GC = WL = ε ox t ox 15 [t ox -> TOX in SPICE] [ -> COX in SPICE] V SB = 0 V, ε Si = 1.06 pf/cm, q = 1.6 x C, N A, φ F => x d = 6.22 µm, N SUB ε Si, x d => C j = 0.17 x 10-8 F/cm 2 [N SUB -> NSUB in SPICE] (p - substrate) W x L = 50 µm x 50 µm => C BC = 42.5 ff
15 Threshold Voltage for MOS Transistors n-channel enhancement [V T0 -> VT0 in SPICE] For V SB = 0, the threshold voltage is denoted as V T0 or V T0n,p 16 Threshold Voltage factors: -> Gate conductor material; -> Gate oxide material & thickness; -> Channel doping; -> Impurities in Si-oxide interface; -> Source-bulk voltage V sb ; -> Temperature. V T0 = Φ GC 2φ F Q B0 Q ox (+ for nmos and - for pmos) Φ GC = φ F (substrate) -φ M Φ GC = φ F (substrate) -φ F (gate) [Q ox = qnss in SPICE] [2φ F = PHI in SPICE] [N A = NSUB in SPICE] metal gate polysilicon gate
16 Threshold Voltage for MOS Transistors n-channel enhancement For : the threshold voltage is denoted as V T or V Tn,p 17 V T = Φ GC 2φ F Q B Q ox where = Φ GC 2φ F Q B0 V T0 Q ox Q B Q B0 (γ = Body-effect coefficient) [γ = GAMMA in SPICE] +
17 Threshold Voltage for MOS Transistors 18 n-channel -> p-channel ****BE CAREFULL*** WITH SIGNS φ F is negative in nmos, positive in pmos Q B0, Q B are negtive in nmos, positive in pmos γ is positive in nmos, negative in pmos V SB is negative in nmos, positive in pmos NOTE: γ C BC C GC
18 Threshold Voltage for MOS Transistors 19 3V V T0 nmos N BULK = N A pmos N ABULK -3V N BULK = N D 3V V T 16 3 (nmos 10 /cm ) 14 (nmos 3 x10 /cm 3) (pmos 10 /cm ) 6 V BS SB -3V
19 EXAMPLE 3.2 Calculate the threshold voltage V T0 at V BS = 0, for a polysilicon gate n-channel MOS transistor with the following parameters: substrate doping density N A = cm -3, polysilicon doping density N D = 2 x cm -3, gate oxide thickness t ox = 500 Angstroms, oxide-interface fixed charge density N ox = 4 x cm φ F(sub), Φ GC : V T0 = Φ GC 2φ F(sub) Q B0 Φ GC = φ F(sub) φ F(gate) Q ox φ F(sub) = kt q ln n i = 0.026Vln 1.45x1010 N A = 0.35V φ F(gate) = kt q ln N D n i 2x10 20 = 0.026Vln 1.45x10 10 = 0.60V Φ GC = φ F(sub) φ F(gate) = V V = V
20 EXAMPLE 3-2 CONT. Q B0 : V T0 = Φ GC 2φ F(sub) Q B0 Q ox 21 : Q ox : = 2(1.6x10 19 C)(10 16 cm 3 )(1.06 x10 12 Fcm 1 ) 2x0.35V F = C/V = x 10-8 C/cm 2 = ε ox t ox = 0.34x10 12 Fcm 1 500x10 8 cm = 6.8x10 8 F/cm 2 Q ox = qn ox = (1.6x10 19 C)(4 x10 10 cm 2 ) = 6.4x10 9 C/cm 2 Q B0 = 4.87x10 8 C/cm 2 6.8x10 8 F/cm 2 = 0.716V Q ox = 6.4x10 9 C/cm 2 6.8x10 8 F/cm 2 = 0.094V V T0 = 0.95V ( 0.70V) ( 0.72V) (0.09V) = 0.38V
21 EXAMPLE 3.3 Consider the n-channel MOS transistor with the following process parameters: substrate doping density N A = cm -3, polysilicon doping density N D = 2 x cm -3, gate oxide thickness t ox = 500 Angstroms, oxide-interface fixed charge density N ox = 4 x cm -2. In digital circuit design, the condition V SB = 0 can not always be quaranteed for all transistors. Plot the threshold voltage V T as a function of V SB. 22 γ - Body-effect coefficient: γ = F = C/V 2qN e A Si = 2(1.6 x10 19 C)(10 16 cm 3 )(1.06 x10 12 Fcm 1 ) 6.8x10 8 F/cm 2 = 5.824x10 8 C/V 1/ 2 cm 2 6.8x10 8 C/Vcm 2 = 0.85V 1/ 2
22 EXAMPLE 3-3 CONT. 23 where VT0 = 0.38V (from EX 3-2) γ = 0.85V 1/ V T (Volts) V SB (Volts)
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 2017 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2017 Khanna Lecture Outline! Semiconductor Physics " Band gaps "
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationESE 570 MOS TRANSISTOR THEORY Part 1. Kenneth R. Laker, University of Pennsylvania, updated 5Feb15
ESE 570 MOS TRANSISTOR THEORY Part 1 TwoTerminal MOS Structure 2 GATE Si Oxide interface n n Mass Action Law VB 2 Chemical Periodic Table Donors American Chemical Society (ACS) Acceptors Metalloids 3 Ideal
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 29, 2019 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2019 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOSFET N-Type, P-Type. Semiconductor Physics.
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 217 MOS Transistor Theory, MOS Model Lecture Outline! Semiconductor Physics " Band gaps " Field Effects! MOS Physics " Cutoff
More information! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!
More information! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 9, 019 MOS Transistor Theory, MOS Model Lecture Outline CMOS Process Enhancements Semiconductor Physics Band gaps Field Effects
More informationFIELD-EFFECT TRANSISTORS
FIEL-EFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancement-type N-MOS transistor 3 I-V characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation
More informationElectrical Characteristics of MOS Devices
Electrical Characteristics of MOS Devices The MOS Capacitor Voltage components Accumulation, Depletion, Inversion Modes Effect of channel bias and substrate bias Effect of gate oide charges Threshold-voltage
More informationLecture 12: MOS Capacitors, transistors. Context
Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those
More informationLecture 12: MOSFET Devices
Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background
More informationMOS Transistor I-V Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationEE 560 MOS TRANSISTOR THEORY PART 2. Kenneth R. Laker, University of Pennsylvania
1 EE 560 MOS TRANSISTOR THEORY PART nmos TRANSISTOR IN LINEAR REGION V S = 0 V G > V T0 channel SiO V D = small 4 C GC C BC substrate depletion region or bulk B p nmos TRANSISTOR AT EDGE OF SATURATION
More informationLecture 11: MOS Transistor
Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Cross-section and layout
More informationLecture 04 Review of MOSFET
ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D
More informationCMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!
More informationLecture 3: CMOS Transistor Theory
Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors
More informationMOS Capacitor MOSFET Devices. MOSFET s. INEL Solid State Electronics. Manuel Toledo Quiñones. ECE Dept. UPRM.
INEL 6055 - Solid State Electronics ECE Dept. UPRM 20th March 2006 Definitions MOS Capacitor Isolated Metal, SiO 2, Si Threshold Voltage qφ m metal d vacuum level SiO qχ 2 E g /2 qφ F E C E i E F E v qφ
More informationEE105 - Fall 2006 Microelectronic Devices and Circuits
EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM
More informationECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
More informationP. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions
P. R. Nelson 1 ECE418 - VLSI Midterm Exam Solutions 1. (8 points) Draw the cross-section view for A-A. The cross-section view is as shown below.. ( points) Can you tell which of the metal1 regions is the
More informationECE-305: Fall 2017 MOS Capacitors and Transistors
ECE-305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel Electrical and Computer Engineering Purdue
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationLecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationPractice 3: Semiconductors
Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given
More informationUniversity of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA
University of Pennsylvania Department of Electrical Engineering ESE 570 Midterm Exam March 4, 03 FORMULAS AND DATA. PHYSICAL CONSTANTS: n i = intrinsic concentration undoped) silicon =.45 x 0 0 cm -3 @
More informationMOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET. MOS Symbols and Characteristics. nmos Enhancement Transistor
MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET Calculation of t and Important 2 nd Order Effects SmallSignal Signal MOSFET Model Summary Material from: CMOS LSI Design By Weste
More informationFundamentals of the Metal Oxide Semiconductor Field-Effect Transistor
Triode Working FET Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationSemiconductor Devices. C. Hu: Modern Semiconductor Devices for Integrated Circuits Chapter 5
Semiconductor Devices C. Hu: Modern Semiconductor Devices for Integrated Circuits Chapter 5 Global leader in environmental and industrial measurement Wednesday 3.2. afternoon Tour around facilities & lecture
More informationECE-305: Fall 2017 Metal Oxide Semiconductor Devices
C-305: Fall 2017 Metal Oxide Semiconductor Devices Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel lectrical and Computer ngineering Purdue
More informationII III IV V VI B C N. Al Si P S. Zn Ga Ge As Se Cd In Sn Sb Te. Silicon (Si) the dominating material in IC manufacturing
II III IV V VI B N Al Si P S Zn Ga Ge As Se d In Sn Sb Te Silicon (Si) the dominating material in I manufacturing ompound semiconductors III - V group: GaAs GaN GaSb GaP InAs InP InSb... The Energy Band
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More informationThe Devices: MOS Transistors
The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor
More informationCHAPTER 5 MOS FIELD-EFFECT TRANSISTORS
CHAPTER 5 MOS FIELD-EFFECT TRANSISTORS 5.1 The MOS capacitor 5.2 The enhancement-type N-MOS transistor 5.3 I-V characteristics of enhancement mode MOSFETS 5.4 The PMOS transistor and CMOS technology 5.5
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationChapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 2 CMOS Transistor Theory Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor Jin-Fu Li, EE,
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)
1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University
NAME: PUID: : ECE 305 Exam 5 SOLUTIONS: April 17, 2015 Mark Lundstrom Purdue University This is a closed book exam. You may use a calculator and the formula sheet at the end of this exam. Following the
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationThe Intrinsic Silicon
The Intrinsic ilicon Thermally generated electrons and holes Carrier concentration p i =n i ni=1.45x10 10 cm-3 @ room temp Generally: n i = 3.1X10 16 T 3/2 e -1.21/2KT cm -3 T= temperature in K o (egrees
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More informationLecture 5: CMOS Transistor Theory
Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos I-V Characteristics
More informationan introduction to Semiconductor Devices
an introduction to Semiconductor Devices Donald A. Neamen Chapter 6 Fundamentals of the Metal-Oxide-Semiconductor Field-Effect Transistor Introduction: Chapter 6 1. MOSFET Structure 2. MOS Capacitor -
More informationSECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University
NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula
More informationEE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing
EE115C Winter 2017 Digital Electronic Circuits Lecture 3: MOS RC Model, CMOS Manufacturing Agenda MOS Transistor: RC Model (pp. 104-113) S R on D CMOS Manufacturing Process (pp. 36-46) S S C GS G G C GD
More information6.012 Electronic Devices and Circuits Spring 2005
6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOS Capacitor with External Bias
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 5: Januar 6, 17 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation! Level
More informationChapter 2 MOS Transistor theory
Chapter MOS Transistor theory.1 Introduction An MOS transistor is a majority-carrier device, which the current a conductg channel between the source and the dra is modulated by a voltage applied to the
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type
More informationDigital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon
More informationPart 4: Heterojunctions - MOS Devices. MOSFET Current Voltage Characteristics
MOS Device Uses: Part 4: Heterojunctions - MOS Devices MOSCAP capacitor: storing charge, charge-coupled device (CCD), etc. MOSFET transistor: switch, current amplifier, dynamic random access memory (DRAM-volatile),
More informationLecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:
Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)
More informationIntroduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline
Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and
More informationMicroelectronics Part 1: Main CMOS circuits design rules
GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! med-amine.miled@polymtl.ca!
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ual-well Trench-Isolated
More informationLecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor
Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE15 Spring 28 Lecture
More informationMOS Transistor Properties Review
MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO
More informationVLSI Design The MOS Transistor
VLSI Design The MOS Transistor Frank Sill Torres Universidade Federal de Minas Gerais (UFMG), Brazil VLSI Design: CMOS Technology 1 Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V
More informationN Channel MOSFET level 3
N Channel MOSFET level 3 mosn3 NSource NBulk NSource NBulk NSource NBulk NSource (a) (b) (c) (d) NBulk Figure 1: MOSFET Types Form: mosn3: instance name n 1 n n 3 n n 1 is the drain node, n is the gate
More information! MOS Capacitances. " Extrinsic. " Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February, 07 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance Model!
More informationChapter 4 Field-Effect Transistors
Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More informationSemiconductor Physics Problems 2015
Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and M-K Lee 1. The purest semiconductor crystals it is possible
More informationFinal Examination EE 130 December 16, 1997 Time allotted: 180 minutes
Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and cross-sectional area 100µm 2
More informationLecture 7 PN Junction and MOS Electrostatics(IV) Metal Oxide Semiconductor Structure (contd.)
Lecture 7 PN Junction and MOS Electrostatics(IV) Metal Oxide Semiconductor Structure (contd.) Outline 1. Overview of MOS electrostatics under bias 2. Depletion regime 3. Flatband 4. Accumulation regime
More informationECE 340 Lecture 39 : MOS Capacitor II
ECE 340 Lecture 39 : MOS Capacitor II Class Outline: Effects of Real Surfaces Threshold Voltage MOS Capacitance-Voltage Analysis Things you should know when you leave Key Questions What are the effects
More informationLecture 7 MOS Capacitor
EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 7 MOS Capacitor Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030
More informationThe Devices. Devices
The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ Field-Oxyde (SiO 2 ) p-substrate p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor Cross-Section of CMOS Technology MOS transistors
More informationEE105 - Fall 2005 Microelectronic Devices and Circuits
EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture
More informationLecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor
Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics t ti Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE105 Fall 2007
More informationEECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 10/30/2007 MOSFETs Lecture 4 Reading: Chapter 17, 19 Announcements The next HW set is due on Thursday. Midterm 2 is next week!!!! Threshold and Subthreshold
More informationELEC 3908, Physical Electronics, Lecture 26. MOSFET Small Signal Modelling
ELEC 3908, Physical Electronics, Lecture 26 MOSFET Small Signal Modelling Lecture Outline MOSFET small signal behavior will be considered in the same way as for the diode and BJT Capacitances will be considered
More informationExtensive reading materials on reserve, including
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More information6.012 Electronic Devices and Circuits
Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to
More information! PN Junction. ! MOS Transistor Topology. ! Threshold. ! Operating Regions. " Resistive. " Saturation. " Subthreshold (next class)
ESE370: ircuitlevel Modeling, Design, and Optimization for Digital Systems Lec 7: September 20, 2017 MOS Transistor Operating Regions Part 1 Today! PN Junction! MOS Transistor Topology! Threshold! Operating
More informationEEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring
More informationESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. Refinement. Last Time. No Field. Body Contact
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 10: September 6, 01 MOS Transistor Basics Today MOS Transistor Topology Threshold Operating Regions Resistive Saturation
More informationMOS CAPACITOR AND MOSFET
EE336 Semiconductor Devices 1 MOS CAPACITOR AND MOSFET Dr. Mohammed M. Farag Ideal MOS Capacitor Semiconductor Devices Physics and Technology Chapter 5 EE336 Semiconductor Devices 2 MOS Capacitor Structure
More information1. The MOS Transistor. Electrical Conduction in Solids
Electrical Conduction in Solids!The band diagram describes the energy levels for electron in solids.!the lower filled band is named Valence Band.!The upper vacant band is named conduction band.!the distance
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. EECS 130 Professor Ali Javey Fall 2006
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 130 Professor Ali Javey Fall 2006 Midterm 2 Name: SID: Closed book. Two sheets of notes are
More informationThe Devices. Jan M. Rabaey
The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models
More information1 Name: Student number: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND. Fall :00-11:00
1 Name: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND Final Exam Physics 3000 December 11, 2012 Fall 2012 9:00-11:00 INSTRUCTIONS: 1. Answer all seven (7) questions.
More informationLecture 6: 2D FET Electrostatics
Lecture 6: 2D FET Electrostatics 2016-02-01 Lecture 6, High Speed Devices 2014 1 Lecture 6: III-V FET DC I - MESFETs Reading Guide: Liu: 323-337 (he mainly focuses on the single heterostructure FET) Jena:
More informationCMOS Devices. PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors
CMOS Devices PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors PN Junctions Diffusion causes depletion region D.R. is insulator and establishes barrier
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February 4, 2016 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance
More informationLecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure
Lecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure Outline 1. Introduction to MOS structure 2. Electrostatics of MOS in thermal equilibrium 3. Electrostatics of MOS with
More informationClass 05: Device Physics II
Topics: 1. Introduction 2. NFET Model and Cross Section with Parasitics 3. NFET as a Capacitor 4. Capacitance vs. Voltage Curves 5. NFET as a Capacitor - Band Diagrams at V=0 6. NFET as a Capacitor - Accumulation
More informationDept. of Materials Science and Engineering. Electrical Properties Of Materials
Problem Set 12 Solutions See handout "Part 4: Heterojunctions MOS Devices" (slides 9-18) Using the Boise State Energy Band Diagram program, build the following structure: Gate material: 5nm p + -Poly Si
More informationThe Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two
More informationMOSFET Physics: The Long Channel Approximation
MOSFET Physics: The ong Channel Approximation A basic n-channel MOSFET (Figure 1) consists of two heavily-doped n-type regions, the Source and Drain, that comprise the main terminals of the device. The
More informationEE5311- Digital IC Design
EE5311- Digital IC Design Module 1 - The Transistor Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai October 28, 2017 Janakiraman, IITM
More informationECE321 Electronics I
EE31 Electronics I Lecture 8: MOSET Threshold Voltage and Parasitic apacitances Payman Zarkesh-Ha Office: EE Bldg. 3B Office hours: Tuesday :-3:PM or by appointment E-mail: payman@ece.unm.edu Slide: 1
More informationMOSFET Model with Simple Extraction Procedures, Suitable for Sensitive Analog Simulations
ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY Volume 10, Number 2, 2007, 189 197 MOSFET Model with Simple Extraction Procedures, Suitable for Sensitive Analog Simulations S. EFTIMIE 1, ALEX. RUSU
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS
More informationECEN474/704: (Analog) VLSI Circuit Design Spring 2018
ECEN474/704: (Analog) SI Circuit Design Spring 2018 ecture 2: MOS ransistor Modeling Sam Palermo Analog & Mixed-Signal Center exas A&M University Announcements If you haven t already, turn in your 0.18um
More information