# Semiconductor Physics Problems 2015

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1 Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and M-K Lee 1. The purest semiconductor crystals it is possible to fabricate have about 1 impurity per host atoms. Consider Si and answer the following questions: (a) What is the lowest possible concentration of impurities that we can have in a sample? (b) Is it possible for Si to behave as an intrinsic semiconductor at room temperature? E E C A B C D E F E A E V 0 1 F(E) 2. Consider figurers A-F above. (a) Which of the figures (A-F) best represents a p-type extrinsic semiconductor where all dopants are ionized? (b) Which figure represents the highest n (concentration of electrons in the conduction band)? 3. Consider two samples: an n-type sample of silicon which has a uniform doping density N D = cm 3 of arsenic, and a p-type silicon sample which has N A = cm 3 of boron. Determine the following: (a) Consider the n-type material. Find the temperature at which half the impurity atoms are ionized. Assume that all mobile electrons originate from the dopant impurities. (b) For each material, find the temperature at which the intrinsic concentration n i exceeds the impurity density by a factor of 10. (c) Assume full ionization of impurities. Find the equilibrium minority-carrier concentrations in each material at 300 K. (d) Find the Fermi level referred to the valence band edge E V in each material at 300 K. Find also the Fermi level if both types of impurities are present in the same sample (compensation doping) 1

2 4. (a) Compare the figure above to figure 25 on page 39 in Sze (page 43 in 2nd edition). They essentially show the same kind of data. What is the difference between how data is plotted? Why do you think we prefer the representation above? (b) From the figure above, determine the ionization energy of the donor atoms used to dope the Si sample. 5. Consider the Fermi level for a boron-doped Si sample with an impurity concentration of cm 3 at 300 K. What fraction of the impurity atoms are ionized? Could we just say that all of them are ionized? Hint: select a value for the concentration of ionized acceptors, which also gives you the concentration of holes. Use this to calculate E F. Use this to evaluate the percentage of ionized acceptors from the Fermi distribution, which you can use to evaluate the E F again. If necessary, iterate a few times until consistent. 6. For p in a sample where N A > N D we find p as p = 1 [ ] N A N D + (N A N D ) n 2 i For what doping levels (see below) can we estimate that p = N A N D? Use n i = cm 3 and n i = cm 3 for Si and Ge, respectively. All dopings in cm 3. (a) N A = and N D = , Si sample (b) N A = and N D = , Si sample (c) N A = and N D = , Ge sample (d) N A = and N D = , Ge sample 2

3 7. Consider a compensated (contains both donor and acceptor impurity atoms in the same region) n-type Si sample at T = 300 K, with a conductivity of σ = 16(Ωcm) 1 and an acceptor doping concentration of cm 3. Determine the donor concentration. Assume complete ionization and an electron mobility of µ n = 1500 cm 2 /Vs. n i = cm HAND-IN Consider a Si sample doped with cm 3 of phosphorous atoms, cm 3 of arsenic atoms and cm 3 of boron atoms. Assume that the impurities are completely ionized and the mobilities are µ n = 1500 cm 2 /Vs, µ p = 500 cm 2 /Vs, independent of impurity concentrations. n i = cm 3 in Si at 300 K. (a) Find the resistivity for the sample. (b) Find the Fermi level in the sample. 9. Consider scattering in an n-type semiconductor sample by studying fig 2 on page 46 in Sze (p 50 in 2nd edition). Which of the following statements are true? (a) If doping level is increased a factor 10, conductivity is also increased a factor 10 (b) At high T, lattice/phonon scattering dominates (c) At room temperature, the scattering time due to lattice scattering is longer than that due to impurity scattering in lightly doped samples (d) If we could remove all impurities, the low T scattering time would increase 10. Compute the average thermal velocity (speed) for holes in a Si sample at room temperature. Next assume that we apply a voltage of 1 mv over a 0.2 mm long section of the semiconductor. What is the drift velocity? The hole mobility is 400 cm 2 /Vs. 11. Calculate the electron and hole concentration under steady-state illumination in n-type silicon with excess generation rate G L = cm 3 s 1, N D = cm 3 and τ p = 10µs. 12. HAND-IN Assume that an n-type semiconductor is uniformly illuminated, producing a uniform excess generation rate G. Show that in steady state the change in semiconductor conductivity is given by σ = q(µ n + µ p )τ p G. 3

4 E C E i E F E V 0 L x 13. The energy band diagram for a semiconductor is shown in the figure above. This may for instance represent the variation of potential along the radius of a n-type semiconductor nanowire with the Fermi level pinned close to the valence band edge at the nanowire surface by surface states. Sketch the general form of (a) n and p versus x, (b) the electrostatic potential Ψ as a function of x, (c) the electric field as a function of x, (d) J n and J p versus x. region 1 region 2 N D = cm -3 N A = cm -3 N A = cm Consider a Si pn-junction with impurity concentrations as indicated in the figure above. Compute (a) The minority carrier concentration in region 1 (b) The minority carrier concentration in region 2 In order to compute the built-in potential V bi, V bi = kt q ln X 1X 2 n 2 i which of the following suggestions for X 1 and X 2 would you use? (a) X 1 = N D1 and X 2 = N A2 (b) X 1 = N D1 N A2 and X 2 = N A2 (c) X 1 = N D1 N A1 and X 2 = N A2 (d) X 1 = N D1 and X 2 = N A1 4

5 15. Consider an ideal silicon pn abrupt junction with N A = cm 3 and N D = cm 3. Assume that all impurities are completely ionized. (a) One approach to find the built-in voltage/potential is to consider the p- and n-part of the junction separately. V bi can then be found as the difference between the Fermilevel E F n on the n-side and the Fermi level E F p on the p-side, as qv bi = E F n E F p. Convince yourself that this gives an equation corresponding to equation 12 on page 85 in Sze (p. 91 in 2nd edition). (b) Calculate V bi at T = 300, 350, 400, 450 and 500 K and plot V bi vs T. (c) Try to give a physical explanation for the trend observed in b). Hint: Maybe you can base your reasoning on the procedure in part a). (d) Find the depletion layer width and the maximum field at zero bias for T = 300 K. N D --N A (cm -3 ) x(µm) HAND-IN (a) Find and sketch the charge density, the built-in electric field and the potential for a silicon p-i-n junction with the doping profile shown in the figure above. ( i represents a very lightly doped or nearly intrinsic region.) (b) Calculate Vbi and the length of each depletion region and thermal equilibrium. (c) Compare the maximum field in the pin junction to the maximum field in a pn junction that contains no lightly doped intermediate region, but has the same dopant concentrations as in part (a) in the other regions. (d) Make a sketch indicating how the built-in electrical field in the junction changes when a reverse bias is applied. 5

6 1 2 C j (farads -2 ) V a (volts) 0.8 V 17. HAND-IN The depletion layer capacitance C D (denoted C j in the plot above) of a pn junction diode with area 10 5 cm 2 is measured. A plot of (1/CD 2 ) vs. the applied voltage V a is shown in the figure above. (a) If the diode is considered as a one-sided step junction, where the p-side is heavily doped, find the doping level on the n-side. (b) Sketch (qualitatively) the doping density on the n-side of the p+n junction. Calculate the location of the point (distance from the actual junction) on the n-side at which the dopant density changes, and include this point in your sketch. Indicate how the dopant density changes at this point does it increase or decrease compared to the value you found in a)? R L =100 kω V F =5V V R =10 V 18. HAND-IN In an ideal p + n silicon diode with N D = cm 3 and N A = cm 3 the hole lifetime is 1 µs and their mobility 450 cm 2 /Vs. The area of the diode is 0.1 mm 2. ( Ideal implies that effects within the space-charge region are negligible and that minority carriers flow only by diffusion mechanisms in the charge neutral regions.) (a) Determine the current in the diode when reverse biased as above. (b) Estimate the stored minority carrier charge when the diode is forward biased in the circuit above. (c) Turning the switch will reverse bias the diode. Determine the change in fix charge in the depletion region on the n side when the diode is switched from forward to reverse bias. 6

7 19. Consider an ideal, long-base, silicon abrupt pn-junction diode with uniform cross section and constant doping on either side of the junction. The diode is made from 1 Ω-cm p-type and 0.2 Ω-cm n-type materials in which the minority-carrier lifetimes are τ n = 10 6 s and τ p = 10 8 s, respectively. You may find figure 7 on page 51 of Sze (p 55 in 2nd edition) and fig 3 on page 47 (p 51) useful. (a) What is the value of the built-in voltage (built-in potential)? (b) Calculate the density of the minority carriers at the edge of the space-charge region when the applied voltage is 0,589 V (which is 23kT/q). (c) Sketch the majority- and minority-carrier currents as functions of distance from the junction on both sides of the junction, under the applied bias voltage of part b. (d) Calculate the location(s) of the plane or planes at which the minority-carrier and majority-carrier currents are equal in magnitude for the applied bias of part b. 20. (a) For forward voltages between 0 and 0.6 V, plot (on a logarithmic scale) the diffusion current in a Si p+n-junction. In the same plot, include also the recombination current (eq 59 on page 105, p 110 in 2nd edition). You may assume N D = cm 3, µ p = 500 cm 2 /Vs and D p = 10 cm 2 /s and a life-time τ p = τ = 1µs. For the purpose of calculating the built-in potential you can use for instance N A = cm 3. (b) Finally, plot the sum of the two current contributions, also in the same plot. Try to identify regions with ideality factor 1 or 2 (see page 106 (p 112 in 2nd edition) for definition of ideality factor) 7

8 21. A Si npn transistor has impurity concentrations of cm 3, cm 3 and cm 3 in the emitter, base and collector, respectively. The p-type base width is 1.0 µm, and the device cross-sectional area is 0.2 mm 2. When the emitter-base junction is forward biased to 0.5 V and the base-collector junction is reverse biased to 5 V, calculate (a) the neutral base width and (b) the minority carrier concentration in the base at the edge of the emitter-base junction depletion region. 22. HAND-IN The figure above depicts a pnp bipolar transistor and all the currents which we consider in it. (a) Draw an equivalent figure, still for a pnp-transistor, where you instead of currents draw electron and hole flows. (b) Draw an equivalent figure for a npn transistor, where you draw currents. Label the currents in a way appropriate to the npn-transistor. Make nice big figures, so that everything is clearly visible. 8

9 23. HAND-IN Consider Eq. 14 on p. 130 in Sze (2nd edition; see Eq. (14) p. 138) for the distribution of minority carriers in the base of an pnp bipolar transistor in the active mode (EB junction forward biased and BC junction reverse biased). The equation can be reorganized to read: W x sinh( L p n (x) p n0 = (p n (0) p n0 ) p ) sinh( W + (p n (W ) p n0 ) sinh( x L p ) L p ) sinh( W L p ) where x = 0 and x = W are the edges of the neutral base. (a) For a Si pnp-transistor, plot p n (x)/p n0 as a function of x/w for different values of W. In your plot, include the following neutral base widths W : W/Lp = 100, 10, 5, 2, 1, 0.5, 0.1 and All graphs should be in the same plot (this is why the x-axis should be normalized to x/w ). You can assume V EB = 0.5 V, V CB = 1 V, N B = cm 3 and L p = 10 4 cm (the minority carrier diffusion length in the base). (b) Using the plots in a), evaluate the ratio I Cp /I Ep for the different base widths W. Hint the currents can be obtained by estimating the gradients of the minority carrier distributions. Make a graph where you plot the ratios I Cp /I Ep for different W vs W. Since W varies over four orders of magnitude, you need to use a logarithmic scale on the x- axis. Verify your results by comparing your ratios to the theoretical ratio I Cp /I Ep = 1/ cosh(w/l p ). (c) Write a short text (150 words is sufficient) describing how your plots are significant to our discussion of bipolar transistors. 24. HAND-IN Consider a Si npn transistor. The area of the device is cm 2. In absence of applied bias, the neutral base width is cm. For the transistor we further have: N E = cm 3 N B = cm 3 N C = cm 3 L E = cm L B = cm L C = cm D E = 5.18 cm 2 /s D B = 22 cm 2 /s D C = 15.6 cm 2 /s (a) Calculate I En and I Ep (it is OK to use the expressions for current for short bases, that is, when W/L n < 1). Also calculate the emitter efficiency γ for a forward bias of V EB = 0.6 V on the emitter-base junction. You don t need to care about the change in W due to biasing. (b) What is the emitter efficiency if the emitter is doped to the same level as the base, that is, N E = N B = cm 3? 9

10 25. For the transistor of problem 24, consider the emitter-base junction open-circuited and the base-collector junction reverse biased by -1 V. Find V EB and I CBO (that is the current in the base-collector junction when the emitter current is zero). The neutral base width in the absence of applied biases is stated in problem 24. Here, there is a reverse bias applied to the base-collector junction. Since the collector is lightly doped the depletion region at the base-collector junction will expand mainly into the collector, and thus the base width will not be significantly reduced. You can use the value of problem 24 as the base width W. 26. Consider the lower image on p 57 of the notes. It shows band diagrams for a pnp-transistor in the four modes of operation. Draw the equivalent images for a npn transistor. By equivalent we mean that the axes stay the same, for instance that a positive V EB means V E > V B. This will forward bias the EB-junction in a pnp-transistor, but what is the effect in a npntransistor? V CC = +12 V R C v in R B B C E v out 27. The transistor in the circuit shown in the figure above has a common-emitter current gain β = 100. The resistors in the circuit are R C = 1 kω and R B = 20 kω. Assume V EB = 0.6 V for the forward biased EB junction. Determine v out for v in = 1 V and 2 V. 28. For an ideal MOS with a n-type semiconductor under inversion, plot (a) the space charge distribution (b) the electric field (c) the potential 10

11 29. We want to find the threshold voltage V T for inversion in a p-type Si MOS in terms of material constants, such as dielectric constants, and in terms of parameters that we control, such as doping level. The voltage V T is split between the oxide and the semiconductor, so that V T = Ψ S + V 0. The band bending (in inversion) is primarily given by the depleted region in the semiconductor. Here, we have a space charge density ρ = qn A for 0 x W (see figure). From that we find the potential Ψ(x) = qn A 2ε s (x W ) 2 = Ψ s (1 x W )2 where Ψ s = qn A 2ε s W 2 (a) Deep in the p-type semiconductor p p0 = N A. Start from p = n i e (E i E F )/kt and show that Ψ B = (kt/q) ln(n A /n i ) (b) In strong inversion the electron concentration at the surface n s N A. Starting from n s = n i e (E F E is )/kt, where E is is the intrinsic Fermi level at the surface, show that E F E is = Ψ B when n s = N A. The potential at the surface thus has to be Ψ S = 2Ψ B for inversion. (c) Now consider the voltage drop V o over the oxide. From electrostatics, we found that V o = d Qm ε ox = d Qs ε ox. At the onset of strong inversion, Q s can be approximated by Q sc where Q sc is the charge from the depleted acceptors. In inversion, Q sc = qn A W m. Show that the depletion region width W can be written in terms of the surface potential as W = 2εsΨ s qn A W m = 2εs2Ψ B qn A. (see beginning of problem) and that, consequently, in inversion, (d) Now we put our results together. Show that the threshold voltage V T = Ψ s (inv) + V o = 2kT q ln N A ni + 4εsN A d 2 ε 2 ox kt ln N A ni 11

12 E F qψ B E i E F d ψ -V FB 0 W x 30. HAND-IN For the MOS structure above, the work function in the metal is smaller than that of the semiconductor by 1V (we disregard any oxide charges). The potential in the metal relative to in the semiconductor, V F B, is the sum of a potential drop over the oxide and a potential drop over the depleted region of the semiconductor. Consider the semiconductor to be grounded. The oxide thickness d = 10 nm, the oxide permittivity is ε ox = 3.9ε 0 and N A = cm 3. (a) What is the value of the surface potential? (b) What is the electric field in the oxide? (c) What are the values of electron and hole concentrations at the surface of the semiconductor? 31. Consider a MOS device on a p-type substrate (N A = cm 3 ) with 20 nm of gate oxide. The gate is made of polycrystalline n+-si. When used as a gate electrode, the n+- Si is very heavily doped and essentially the Fermi level coincides with the conduction band edge. (a) Find the work function difference between the polycrystalline Si gate and the p-type Si semiconductor. (b) Find V T. (c) Make a sketch of the C V curve measured at high frequencies. In your sketch, label (roughly) V T and V F B. (d) Calculate C min and C max (still for high frequency). 12

13 32. A Si MOSFET has the following dimensions and characteristic parameters: L = 1 µm, Z = 1 µm, N A = cm 3, µ n = 800 cm 2 /Vs and the Si oxide thickness is 20 nm. The semiconductor work function is 3.8 V and the gate work function is 4 V. (a) Sketch the band diagram at thermal equilibrium and at threshold condition Ψ s = 2Ψ B. What is the threshold voltage? (b) Calculate the drain current for V G = 2.2 V and V D = 0.3 V. (c) Calculate the drain current for V G = 2.5 V and V D = 0.3 V. 33. A n-channel MOSFET is made on p-type silicon with N A = cm 3. (a) Determine the threshold voltage under the assumption that the oxide (rel. dielectric constant 3.9) is free of charge and that difference in work functions may be neglected. The gate oxide is 100 nm thick. (b) Sketch the drain current vs the gate voltage for the MOSFET of part a) if drain and gate are connected and source and substrate are grounded. Can the threshold voltage be determined from the characteristic? 34. Threshold voltage control is an important concept. In devices such as CMOS (Complimentary MOS one PMOS and one NMOS acting together as for instance an inverter) and generally in circuits, we may want to tailor the threshold voltage. There are several approaches to this. Consider a N-MOS with gate and semiconductor parameters as in problem 31. (a) Is the N-MOS conducting at V G = 0? (b) Find the change in doping necessary to change V T by 0.5 V. Here, we assume that the doping is changed to a large depth in the semiconductor, not only just below the oxide. (c) Find the change in oxide thickness needed to accomplish the same shift of V T as in b) 13

14 35. HAND-IN A MOSFET has a threshold voltage of V T = 0.5 V, a subthreshold swing of 100 mv/decade, and a drain current of 0.1 ma at V T. (a) What is the subthreshold leakage current at V G = 0V? (Hint: think about what the subthreshold swing really means.) (b) In the MOSFET lab, you measured drain current as a function of gate and drain voltage. The figure shows the drain current at a fixed V D > V Dsat ) for varying V G for one of the devices in the lab. Was it the NMOS or the PMOS and what is the subthreshold swing? drain current /A (absolute value) gate voltage / V 14

15 36. HAND-IN (a) Find the barrier height and the donor concentration of the W- GaAs Schottky barrier shown in the capacitance plot above left. (b) Compare the barrier height with that obtained from the saturation current density shown in the current plot above right, assuming that A = 4 A/(cm-K) Compare a Schottky diode fabricated on n-gaas and a p+n diode (also GaAs). The reverse saturation currents are I s = A and I 0 = A for the Schottky diode and the pn-junction, respectively. What voltage is required for each device in order to have 0.5 ma pass through it? 38. This problem concerns the discussion in the Sze e-book (which is linked from the course homepage). The relevant pages are See also notes. (a) In figure 6 on page 143 we notice that c 2 = 0.27 is relevant for Si. This number thus tells us something about the nature of the population of surface states in Si. Assuming an interface layer with thickness δ = 5Å and permittivity ε i = ε 0 and a semiconductor doping of N D = cm 3, calculate the density of interface states D it. (check your answer on page 142). (b) If the Fermi level does not coincide with the neutral level, there will be a net charge at the interface. By how much can the Fermi level deviate from the neutral level in order for the interface charge Q ss to not become greater than the semiconductor charge Q sc (from ionized dopants)? Here you will have to obtain a value for V bi (Ψ bi ) at some point. Either you can just assume some reasonable value, or use fig. 5 on page 140 in the book. Ψ bi = E g qφ n qφ 0, if we make the approximation that E F coincides with φ 0 (not completely true, but not far from the truth either, it will do as an estimate). φ 0 is calculated at the bottom of p

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