6.012 Electronic Devices and Circuits Spring 2005


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1 6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) OPEN BOOK Problem NAME RECITATION TIME Total General guidelines (please read carefully before starting): Make sure to write your name on the space provided above. All answers should be given in the space provided. Please do not turn in any extra material. If you need more space, use the back page. You have 180 minutes to complete the quiz. Where required, make reasonable approximations and state them. Partial credit will be given for setting up problems without calculations. NO credit will be given for answers without reasons. Use the symbols utilized in class for the various physical parameters, i.e. N d, n o, etc. Every numerical answer must have the proper units next to it. Points will be subtracted for answers without units or with wrong units. Use the following fundamental constants and physical parameters for silicon at room temperature. n i = 1.0 x cm 3 kt/q = 0.025V q = 1.6 x C ε S = 1.0 x F/cm ε OX = 3.45 x F/cm 1
2 Problem 1 [40 points] An ideal nmosfet has transconductance, g m characteristics as shown below: g m V BS = 0V V DS = 1V V GS In addition, C g is measured to be pF at V DS = 0V, V GS = 3V, V BS = 0V. W = 10μm and L = 5μm. Neglect channel length modulation and neglect any overlap capacitances. Assume N a = cm 3. a) On the axes below, draw the g m characteristic for V DS = 2V and V BS = 0V. Label the various regions of operation and any breakpoints on the plot. g m V DS = 1V V GS 2
3 b) Find the oxide thickness, t ox. c) Find the electron mobility, μ n. 3
4 I D d) On the axes below, sketch I D vs. V GS for V DS = 1V, V BS = 3.0V. Label the regions of operation of the device, and the value of I D at V GS = 3V V GS 4
5 e) Another nmosfet is now fabricated with the same W, L, and N a. A new gate dielectric material is used, with dielectric constant ε new = 2 ε ox, and thickness t new = 2t ox. The electron mobility for the device with the new gate dielectric is half that of a MOSFET fabricated with silicon dioxide, i.e. μ new = 1/2 μ n (oxide). For each of the following, assume the same bias for each device, and circle one of the choices, giving a brief justification: i) V T for the new device, relative to the oxidedielectric device is: lower higher the same ii) g msat for the new MOSFET, relative to the oxidedielectric device is: lower higher the same 5
6 iii) g mb for the new MOSFET, relative to the oxidedielectric device is: lower higher the same iv) C g for V GS = 0V and V DS = 0V for the new device, relative to the oxidedielectric device is: lower higher the same 6
7 Problem 2 [40 Points] A Bipolar transistor is biased to form a simple current amplifier. We are assuming no loading (R S, R L 0) as shown below: The minority carrier concentration profiles are shown on a linear scale at the DC operating point. A e = 10μm x 10μm D n = 10cm 2 /s D p = 5cm 2 /s cm cm μm 0.2μm a) From the information given above, calculate I BIAS. 7
8 b) Calculate the DC collector current I C. c) Assuming the depletion capacitances, C je and C bc are negligible, find the frequency at which the magnitude of the current gain is unity, f = f T. 8
9 d) From the information given, find β o and f 3dB for the Bode Plot shown below. I out I s β o 1 f 3dB f T f e) Given an input signal in the time domain f T i S (t) = 1μA COS (2π ( 10 )) t calculate the amplitude of the sinusoid at the output. 9
10 Problem 3 [40 Points] Consider the following amplifier circuit: Bipolar Device Data I S = A β o = 100 V A (r o ) C π = 200fF C μ = 20fF Diode Device Data I o = A a) Determine V BIAS such that V OUT = 0 when V S = 0V. Assume the BJT is in the forward active region and ignore base current for this calculation. 10
11 b) Sketch an appropriate small signal model to determine the overall low frequency gain including R L. c) Calculate the overall low frequency voltage gain using the model you sketched in part (b). State any simplifying assumptions. 11
12 d) Sketch a small signal model that includes C π and Cμ. e) Using the Miller Theorem, calculate the Miller capacitance numerical value. 12
13 Problem 4 [40 Points] You are given a CS amplifier driving a purely capacitive load as shown below with the NMOS and PMOS device data. Assume all transistors are in the saturated region and assume all sources are shorted to the backgate. Device Data V tn = 0.5V V tp = 0.5V μ n C ox = 50μA/V 2 μ p C ox = 25μA/V 2 For W/L = 150/1.5 C gd = 150fF C gs = 350fF Neglect channel length modulation for part a & b. a) Calculate the value of I to make the pchannel supply current source for the CS amplifier have a value of 100μA. 13
14 b) Calculate V BIAS such that the NMOS drain current is equal to I SUP = 100 μa. c) Calculate the transconductance of the CS amplifier at the operating point set in a & b. 14
15 d) Given that the low frequency voltage gain is 50, calculate R out and (λ n +λ p ). Do not assume any particular λ. e) A twoport model for the CS amplifier with capacitors added is shown below. Using the Miller Theorem and Method of Open Circuit Time Constants, find ω 3dB. 15
16 f) The width of the pchannel supply current source in the CS amplifier is reduced from 150μm to 1.5μm and the reference current source value remains I. Estimate the new low frequency voltage gain. g) Estimate the new ω 3dB with the smaller (1.5μm) pchannel current source. State assumptions to reduce the amount of work you do for this part. 16
17 Problem 5 [40 Points] You are given a multistage voltage amplifier shown below. Assume that all devices are in their constant current region (MOSsaturated, BJTforward active), at the operating point set by V BIAS. Assume all substrates are shorted to their source. Device Data R L V Tp = μ p C ox = 25μA/V 2 λ P = 0 v out ß o = 100 V A = 10V  a) Identify the type of stage (e.g. CS, CD) and the numerical value of the supply current sources for stages 1 and 2. 17
18 b) A small signal twoport model of both stages including R S and R L is shown below. Calculate R in1, A v1, and R out1 v s 18
19 c) Calculate R in2, A v2, and R out2. d) Given R S = 20kΩ, adjust the width of the pchannel stage 1 supply current source such that 50% of the voltage enters the amplifier. 19
20 e) Given R L = 500Ω adjust the width of the pchannel stage 2 supply current source such that 50% of the voltage is transferred to the load. f) What is the overall voltage gain v out /v s [assuming the pchannel current sources are sized as in (d) and (e) above]? 20
21 MIT OpenCourseWare Microelectronic Devices and Circuits Spring 2009 For information about citing these materials or our Terms of Use, visit:
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