The Devices: MOS Transistors


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1 The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, AddisonWesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall
2 NMOS Transistor Gate Oxide Field Oxide CROSSSECTION of NMOS Transistor
3 CrossSection of CMOS Technology
4 CurrentVoltage Relations V GS V V DS I D  + V(x) L x At x, the gate to channel voltage equals V GS  V(x)
5 Transistor in Linear Region Assume that the voltage exceeds V T all along the channel Induced charge/area at point x Current Qi ( x) Cox[ VGS V( x) VT ] ID vn ( x). Qi ( x). W v n (x) : drift velocity Id dx n. Cox. W( VGS V VT ) dv Integrating over the length of the channel L v n E( x) n n dv dx I D K' K' n n n W L ox (( V GS C n V C T ox ox T ). V DS 2 DS V 2 )
6 Transistor In Saturation
7 Transistor in Saturation If drainsource voltage increases, the assumption that the channel voltage is larger than V T all along the channel ceases to hold. When V GS  V(x) < V T pinchoff occurs Pinchoff condition V GS V DS V T
8 Saturation Current The voltage difference over the induced channel (from pinchoff to the source) remains fixed at V GS  V T and hence, the current remains constant. Replacing V DS by V GS V T in equation for I D yields I D K' 2 n W L ( V GS V T 2 ) Effective length of the conductive channel is modulated by applied V DS  Channel Length Modulation
9 CurrentVoltage Relations Cutoff: V GS V T, I DS 0 Linear Region: V DS < V GS  V T I k' n D k C n ' n W L ox DS V 2 GS VT VDS n t ox ox V 2 Process Transconductance Parameter Saturation Mode: V DS V GS  V T Channel Length Modulation I D k' n W 2 GS T 1 2 L V V V DS
10 IV Relations Linear: V DS < V GS  V T Linear (a) ID as a function of VDS I D (b) as a function of V GS (for V DS = 5V) NMOS Enhancement Transistor: W = 100 m,l = 20 m
11 Threshold Voltage: Concept V T = V FB + V B + V ox V B = 2f F (strong inversion)
12 MOSCAP Band Diagrams
13 Energy band diagram E vac Vacuum Level 0.95 ev qϕ m = 4.1 ev E c qχ = 4.05 ev qϕ s E f 89 ev E c E f E g = 1.12 ev Metal (aluminum) E v Ptype silicon E v qϕ s = qχ + Eg/2 + qϕ B Silicon Dioxide
14 MOScap: Equilibrium E vac qϕ m qϕ s Here, ϕ m = ϕ s Flat band condition E f E c E f ϕ s can be changed with doping Gate Ptype Si E v Bands will not be flat if ϕ m ϕ s  apply a negative voltage (ϕ m  ϕ s ) with respect to Si substrate M O S
15 MOScap: Accumulation Negative gate voltage Surface potential (ψ s ) < 0 Bands bend upwards E f V g < E c Gate E f ψ (bulk) = 0 E v Accumulation of holes No band bending deep in the bulk The electric field causes band bending Electric field at any point is the slope of E c or E v at that point The electrostatic potential (ψ) at any point is the net band bending at that point
16 MOScap: Depletion Positive gate voltage V g > 0 Surface potential (ψ s ) > 0 E c E f ψ (bulk) = 0 E f + + E v Gate Depletion region For a small positive gate bias: Bands bend downwards at the surface i.e. E v moves away from E f Majority carriers (holes) are depleted at the surface
17 MOScap: Inversion Surface potential (ψ s ) > 0 Inversion layer at the surface E c ψ (bulk) = 0 V g > E f E f Gate E v Channel at the surface is inverted when (ψ s = 2ψ B ) ( inv) 2 s B kbt 2 q ln N n Where, N a = Doping density in the bulk (cm 3 ) n i = Intrinsic carrier concentration ~ 10E10 (cm 3 ) i a
18 Threshold Adjustment by Ion Implantation Implant a relatively small, precisely controlled number of either boron or phosphorus ions into the nearsurface region of semiconductor Implantation of boron causes a positive shift in threshold voltage Implantation of phosphorus causes a negative shift Like placing additional fixed charges V Q C I ox Q I qn I ( ) : donor ( ) : acceptor
19 Back Biasing or Body Effect V SB is normally positive for nchannel devices, negative for pchannel devices Always increases the magnitude of the ideal device threshold voltage Inversion occurs at f S = (2f F + V SB ) Increases the charges stored in depletion region Q B 2qN A si(2f F VSB)
20 Threshold voltage V T V FB V B V ox V T ms Q C I ox 2 F Q C B ox
21 Dynamic Behavior of MOS Transistor Source of Cap.  Basic MOS structure  channel charge  depletion region of resource bias pn junctions
22 The Gate Capacitance C gdo Lateral diffusion (a) Top view C GSO (b) Crosssection s C gate t ox ox WL C SB P C DB Can be decomposed into a number of elements each with a different behavior
23 The Gate Capacitance Parasitic capacitance between gate and source (drain) called Overlap Capacitance (linear) C gso = C gdo = C ox.x d.w = C o.w Channel Capacitance: C gs, C gd, and C gb CutOff: no channel, total capacitance = C ox WL eff appears between gate and bulk Triode Region: Inversion layer  acts as conductor C gb 0 Saturation: Pinch off, Symmetry dictates C gd 0, C 0 gb C gs C gd C ox WL 2 eff C gs averages (2/3)C ox WL eff
24 Diffusion Capacitance (Junction Capacitance) Reverse biased sourcebulk and drainbulk pn junctions
25 Diffusion Capacitance (Junction Capacitance)  Bottom plate C bottom = C j WL s,  Sidewall junctions  formed by source (N D ) and P + channel stop (N A+ ) C sw = C jsw x j (w+2l s ) = C jsw (W + 2L s )  graded junction (m=1/3) C jsw = C jsw x j, x j = junction depth  C diff = C bottom + C sw = C j * Area + C jsw x Perimeter = C j L s W + C jsw (2L s + W)
26 Junction Capacitance V D (V) C j C j0 ( 1VD / 0 f ) m
27 The SubMicron MOS Transistor Threshold Variations (Manufacturing tech., V SB ) Parasitic Resistances Velocity Saturation and Mobility Degradation Subthreshold Conduction Latchup
28 Threshold Variations In derivation of V T the following assumption were made: charge beneath gate originates from MOS field effects ignores depletion region the source and drain junctions (reverse biased) A part of the region below the gate is already depleted (by source & drain fields), a smaller V T suffices to cause strong inversion V T decreases with L Similar effect can be obtained by increasing V DS or V DB as it increases drainjunction depletion region V T V T Long channel L Low V DS Low L V DS DIBL (Drain Induced Barrier Lowering)
29 Threshold Variations V T can also drift over time (Hotcarrier effect) Decreased device dimensions Increase in electrical field Increasing velocity of electrons, can leave Si surface and enter gate oxide Electrons trapped in gate oxide change V T (increases in NMOS, decreases in PMOS) For a electron to be hot, electric field of 10 4 V/cm is necessary Condition easily met for submicron devices
30 Parasitic Resistances R L W S R[] R C Solutions: cover the diffusion regions with lowresistivity material such as titanium or tungsten, or make the transistor wider
31 Velocity Saturation (1) short channel devices cm/sec (a) Velocity saturation (b) Mobility degradation
32 Velocity Saturation (2) I DSAT v SAT C ox W V ( GS VDSAT VT ) Linear Dependence on V GS independent on L current drive cannot be improved by decreasing L
33 Subthreshold Conduction I D K e ( V V ) q/ nkt V q/ kt gs t (1 e ds ) V GS < V T SOI has better subthreshold leakage d dv (Inverse) Rate of decrease of current : ln( I ) D ln10(1 ) GS 1 KT q 60mV/decade At T= 300 o K
34 Latchup NMOS PMOS S D D S V B > V BE (a) Origin of latchup (b) Equivalent circuit
35 Latchup Parasitic circuit effect Shorting of V DD and V SS lines resulting in chip selfdestruction or system failure with requirements to power down To understand latchup consider: Silicon Controlled Rectifiers (SCRs) Anode A I a I b1 p n p n Cathode C Gate G I c1 I c2 A C G I g I b2 I c
36 Latchup If I g I c2 I c2 is the base current I b1 of the pnp transistor I g I b1 I c1 I b2 (magnitude of current increases) If the gain of the transistor are b 1 and b 2 Then if b 1 b 2 1, the feedback action will turn device ON permanently and current will self destruct device.
37 Latchup Triggering Parasitic npn & pinp has to be triggered and holding state to be maintained Can be triggered by transient currents Voltages during powerup Radiation pulses Voltages or current beyond operating range I ntrigger V pnpon npn. R well Lateral triggering npn : Common base gain of npn transistor Similarly, vertical triggering due to the voltage drop across R substrate as current is injected into the emitter
38 Latchup Triggering Triggering occurs due to (mainly) I/O circuits where internal voltages meet external world and large currents can flow When NMOS experiences undershoot by more than 0.7V, the drain is forward biased, which initiates latchup When PMOS experiences overshoot by more than 0.7V, the drain is forward biased, which initiates latchup
39 Latchup Prevention Analysis of the circuit shows that for latchup to occur the following inequality has to be true ( bnpn 1)( I Rsub I Rwell. b pnp) bnpnb pnp 1 I I where I I I Rsub Rwell DD V benpn R V R sub bepnp well total supply current The feedback current flowing into npn base is collector current offset by I Rsub. To cause the feedback, this current must be greater than initial npn base current, I b. DD Rsub
40 Prevention of latchup Reduce the resistor values (substrate & well) and reduce the gain of parasitic transistors Latchup resistant CMOS process Layout techniques
41 Spice Models Level 1: Long Channel Equations  Very Simple Level 2: Physical Model  Includes Velocity Saturation and Threshold Variations Level 3: SemiEmperical  Based on curve fitting to measured devices Level 4 (BSIM): EmpericalSimple and Popular
42 Main MOS Spice Parameters
43 SPICE Parameters for Parasitics
44 SPICE Transistor Parameters
45 Technology Evolution
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