Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline


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1 Introduction to MOS VLSI Design hapter : MOS Transistor Theory Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and Diffusion apacitance Pass Transistors R Delay Models Slide 1
2 Introduction So far, we have treated transistors as ideal switches An ON transistor passes a finite amount of current Depends on terminal voltages Derive currentvoltage (IV) relationships Transistor gate, source, drain all have capacitance I = (ΔV/Δt) > Δt = (/I) ΔV apacitance and current determine speed Also explore what a degraded level really means Slide 3 MOS apacitor Gate and body form MOS capacitor Operating modes Accumulation Depletion Inversion (a) V g <0 + polysilicon gate silicon dioxide insulator 0 < V g < V t depletion region + (b) V g > V t + inversion region depletion region (c) Slide 4
3 Terminal Voltages Mode of operation depends on V g, V d, V s V gs = V g V s V gd = V g V d gs V ds = V d V s = V gs V gd V s Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage Hence V ds 0 nmos body is grounded. First assume source is 0 too. Three regions of operation utoff Linear Saturation V g + + V gs Vgd gd V ds + V d Slide 5 No channel I ds = 0 nmos utoff V gs = 0 + g + V gd s n+ n+ b d Slide 6 3
4 nmos Linear hannel forms urrent flows from d to s e from s to d I ds increases with V ds Similar to linear resistor V gs > V t + s n+ n+ b g + V gd = V gs d V ds = 0 V gs > V t + s g V > V > V gs gd t + d I ds n+ n+ 0 < V ds < V gs V t b Slide 7 nmos Saturation hannel pinches off I ds independent of V ds We say current saturates Similar to current source V gs > V t + g V + gd < V t s d I ds n+ n+ b V ds > V gs V t Slide 8 4
5 IV haracteristics In Linear region, I ds depends on How much charge is in the channel? How fast is the charge moving? Slide 9 hannel harge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = polysilicon gate t ox n+ L n+ W SiO gate oxide (good insulator, ε ox = 3.9) + gate V g + source g V gd drain channel n+ + n+ V s V ds V d Slide 10 5
6 hannel harge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = V = polysilicon gate t ox n+ L n+ W SiO gate oxide (good insulator, ε ox = 3.9) + gate V g + source g V gd drain channel n+ + n+ V s V ds V d Slide 11 hannel harge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = V = g = ε ox WL/t ox = ox WL ox = ε ox / t ox V = polysilicon gate t ox n+ L n+ W SiO gate oxide (good insulator, ε ox = 3.9) + gate V g + source g V gd drain channel n+ + n+ V s V ds V d Slide 1 6
7 hannel harge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = V = g = ε ox WL/t ox = ox WL ox = ε ox / t ox V = V gc V t = (V gs V ds /) V t polysilicon gate t ox n+ L n+ W SiO gate oxide (good insulator, ε ox = 3.9) + gate V g + source g V gd drain channel n+ + n+ V s V ds V d Slide 13 arrier velocity harge is carried by e arrier velocity v proportional to lateral Efield between source and drain v = Slide 14 7
8 arrier velocity harge is carried by e arrier velocity v proportional to lateral Efield between source and drain v = μe μ called mobility E = Slide 15 arrier velocity harge is carried by e arrier velocity v proportional to lateral Efield between source and drain v = μe μ called mobility E = V ds /L Time for carrier to cross channel: t = Slide 16 8
9 arrier velocity harge is carried by e arrier velocity v proportional to lateral Efield between source and drain v = μe μ called mobility E = V ds /L Time for carrier to cross channel: t = L / v Slide 17 nmos Linear IV Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross I ds = Slide 18 9
10 nmos Linear IV Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross I ds Q = t = channel Slide 19 nmos Linear IV Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross Qchannel Ids = t W V = μ ds ox Vgs V t V ds L V β V ds gs V W = t V β = μ ds ox L Slide 0 10
11 nmos Saturation IV If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs V t Now drain voltage no longer increases current I ds = Slide 1 nmos Saturation IV If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs V t Now drain voltage no longer increases current V I = β V V dsat V ds gs t dsat Slide 11
12 nmos Saturation IV If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs V t Now drain voltage no longer increases current V I = β V V dsat V β = ( V gs V t ) ds gs t dsat Slide 3 nmos IV Summary Shockley 1 st order transistor models 0 Vgs < Vt V I = β V V ds V V < V β V V V > V ds gs t ds ds dsat cutoff linear ( ) gs t ds dsat saturatio n Slide 4 1
13 Example We will be using a 0.6 μm process for your project From AMI Semiconductor t ox = 100 Å.5 μ = 350 cm V gs = 5 /V*s V t = 0.7 V 1.5 V gs = 4 Plot I ds vs. V ds V gs = 0, 1,, 3, 4, 5 Use W/L = 4/ λ β = μ = ( ) = μ I ds (ma) A/ V L L L 14 W W W ox 8 1 V gs = V gs = V 0 gs = V ds Slide 5 pmos IV All dopings and voltages are inverted for pmos Mobility μ p is determined by holes Typically 3x lower than that of electrons μ n 10 cm /V*s in AMI 0.6 μm process Thus pmos must be wider to provide same current In this class, assume μ n / μ p = *** plot IV here Slide 6 13
14 apacitance Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important reates channel charge necessary for operation Source and drain have capacitance to body Across reversebiased diodes alled diffusion capacitance because it is associated with source/drain diffusion Slide 7 Gate apacitance Approximate channel as connected to source gs = ε ox WL/t ox = ox WL = permicron W permicron is typically about ff/μm polysilicon gate W t ox n+ L n+ SiO gate oxide (good insulator, ε ox = 3.9ε 0 ) Slide 8 14
15 Diffusion apacitance sb, db Undesirable, called parasitic capacitance apacitance depends on area and perimeter Use small diffusion nodes omparable to g for contacted diff ½ g for uncontacted Varies with process Slide 9 Pass Transistors We have assumed source is grounded What if source > 0? e.g. pass transistor passing Slide 30 15
16 Pass Transistors We have assumed source is grounded What if source > 0? e.g. pass transistor passing V g = If V s > V t, V gs < V t Hence transistor would turn itself off nmos pass transistors pull no higher than V tn alled a degraded 1 Approach degraded value slowly (low I ds ) pmos pass transistors pull no lower than V tp Slide 31 Pass Transistor kts V SS Slide 3 16
17 Pass Transistor kts Vs = V tn VDD Vtn VDDVtn V tn V s = V tp p V tn V tn V SS Slide 33 Effective Resistance Shockley models have limited value Not accurate enough for modern transistors Too complicated for much hand analysis Simplification: treat transistor as resistor Replace I ds (V ds, V gs ) with effective resistance R I ds = V ds /R R averaged across switching of digital gate Too inaccurate to predict current at any given time But good enough to predict R delay Slide 34 17
18 R Delay Model Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nmos has resistance R, capacitance Unit pmos has resistance R, capacitance apacitance proportional to width Resistance inversely proportional to width g d k s g R/k k d s k k Slide 35 g d k s g k s d R/k k k R Values apacitance = g = s = d = ff/μm of gate width Values similar across many processes Resistance R 6 KΩ*μm in 0.6um process Improves with shorter channel lengths Unit transistors May refer to minimum contacted device (4/ λ) Or maybe 1 μm wide device Doesn t matter as long as you are consistent Slide 36 18
19 Inverter Delay Estimate Estimate the delay of a fanoutof1 inverter A Y 1 1 Slide 37 Inverter Delay Estimate Estimate the delay of a fanoutof1 inverter R A Y 1 1 R Y Slide 38 19
20 Inverter Delay Estimate Estimate the delay of a fanoutof1 inverter R A Y 1 1 R Y R Slide 39 Inverter Delay Estimate Estimate the delay of a fanoutof1 inverter R A Y 1 1 R Y R d = 6R Slide 40 0
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