2.CMOS Transistor Theory

Transcription

1 MOS VLSI esign 2.MOS Transistor Theory Fu yuzhuo School of microelectronics,sjtu Introduction

2 outline P junction principle MOS transistor introduction Ideal I-V characteristics under static conditions Velocity Saturation ynamic haracteristics onideal I-V effects 2/41

3 apacitance Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important reates channel charge necessary for operation Source and drain have capacitance to body Across reverse-biased diodes alled diffusion capacitance because it is associated with source/drain diffusion 3/41

4 iffusion apacitance sb, db Undesirable, called parasitic capacitance apacitance depends on area and perimeter Use small diffusion nodes omparable to g for contacted diff ½ g for uncontacted Varies with process 4/41

5 apacitance components MOS structure capacitances G Overlap cap. hannel capacitances Gate-body cap. S GS G Gate-source cap. SB GB B Gate-drain cap. Junction/diffusion capacitances B Bottom-plate cap. Side-well cap. 5/41

6 The Gate apacitance Polysilicon gate GSO GO ox x d W W o Source n + x d x d W rain n + L d Top view Gate-bulk overlap t ox Gate oxide n + L n + ross section 6/41

7 Gate channel apacitance G G G S G G G S S ut-off Resistive Saturation Most important regions in digital design: saturation and cut-off 7/41

8 Gate apacitance WL ox G WL ox G 2WL ox WL ox 2 G B GS = G WL ox 2 GS G 3 V GS 0 V S /(V GS -V T ) 1 apacitance as a function of V GS (with V S = 0) apacitance as a function of the degree of saturation 8/41

9 Gate apacitance (F) Measuring the Gate ap V GS I G ( V G GS ( V GS ) ) dvgs dt I dv dt GS 8 I V GS (V) 9

10 iffusion Area apacitance hannel-stop implant A 1 Side wall W Source Bottom x j S Side wall Substrate A hannel diff bottom sw j AREA jsw PERIMETER jlsw jsw ( 2L W ) S 10/41

11 An example of iffusion apacitance MOS:t ox =6nm,L=0.24um,W=0.36um,L =L S =0.625um, OX =5.7X10-3 F/m 2, O =3X10-10 F/m, j0 =2X10-3 F/m 2, and jsw0 =2.75X10-10 F/m, determine the zero-bias value of relevant capacitances gc =WL ox =0.24*0.36*5.7=0.49fF overlap =2* o *W=2*0.3*0.36=0.216fF diff-s=ws*j+(w+2s)jsw= 0.36*0.625*2+( *2)*0.275=0.44fF 1F=10 15 ff 11/41

12 etail iffusion apacitance diff-s =W s * js +(W+2 s ) jsw V kt A A ψ0 = ln( 2 ) = 0.026ln( 2 ) q n n sb -M j js = j0(1+ ) ψ0 V sb jsw = jsw0(1+ ) ψ0 -M jsw i i 12/41

13 Junction capacitance comes from A A si j V q A Q 0 Φ 2 A A si j q A 2Φ 0 0 A A si j V q W W W Φ 2 A A si j V q E 0 Φ 2 epletion-region charge Maximum electric field epletion-region width Zero-bias conditons Φ 1 Φ 1 Φ j j A A si j j V V V q A dv dq 13/41

14 Another example alculate the diffusion parasitic db of the drain of a unit-sized contacted nmos transistor in a 0.18um process when the drain is at 0 and at V dd =1.8V, assume the substrate is grounded, the transistor characteristic are j =0.98fF/um 2,M j =0.36, JSW =0.22fF/um,M JSW =0.10, and Ψ 0 =0.75V at room temperature A=20unit 2 =20*0.081=0.162um 2 P=10+4=14unit=14*0.09=1.26um db (0)=0.162* *0.22= db (1.8)=0.162*0.98*(1+1.8/0.75) *0.22*(1+1.8/0.75) /41

15 More detail apacity 0 ) ( ) ( j eq low high low j high j j eq K V V V Q V Q V Q A A si j V q A Q 0 Φ 2 A A si j q A 2Φ 0 0 m low m high low high m eq V V m V V K ) ( ) ( ) )(1 ( diff-s =K eq W s * js +K eqsw (W+2 s ) jsw 15/41

16 apacitance model G GS G GB SB B GSO GO GB Sdiff diff GS G S GS SB B GB G B 16/41

17 The Transistor as a Switch I V GS = V V GS V T R mid S R on R 0 V /2 V V S 17/41

18 The Transistor as a Switch 7 x R eq (Ohm) The resistance is inversely proportional to the W/L ratio of the device For V dd >>V t +V dsat /2, the resistance becomes independent of the supply voltage Once the supply voltage approaches V t, the resistance dramatically increases V (V) 18/41

19 The Transistor as a Switch 19/41

20 Source-rain Resistance R S, L S, W R o R Low-resisitivity material areful layout G Polysilicon gate L rain contact V GS,eff S W R S R rain 20/41

21 outline P junction principle MOS transistor introduction Ideal I-V characteristics under static conditions Velocity Saturation ynamic haracteristics onideal I-V effects 21/41

22 onideal characteristics Velocity saturation hannel length modulation Body effect Threshold Variations Parasitic Resistances Subthreshold onduction Hot-carrier effects Latchup Process variations 22/41

23 hannel length modulation Increasing V S decreases the effective channel length Λ is an empirical channel length, should not be confuse with the symbol used in layout design rules hannel length modulation is very important to analog designers because it reduces the gain of amplifiers, it is generally unimportant for qualitatively understanding the behavior of digital circuit I I ' (1 V S ) 23/41

24 onideal characteristics Velocity saturation hannel length modulation Body effect Threshold Variations Parasitic Resistances Subthreshold onduction Hot-carrier effects Latchup Process variations 24/41

25 Body effect V t = V t0 + γ( -2Φ F +V SB + -2Φ F ) kt A ΦF = ± ln( ) = ± 0.026ln( q n n i i ) γ = t ε ox ox 2qε A = 2qε ox A 25/41

26 An example of Body effect V t = V t0 + γ( -2Φ kt A ΦF = ± ln( ) = ± 0.026ln( q n n i F i +V ) SB γ = - t ε ox ox 2Φ F ) 2qε A = 2qε If nominal threshold voltage of 0.4V and doping level of 8*10 17 cm -3, the body is tied to ground with a substrate contact. how much does the threshold change at room temperature if the source is at 1.1V instead of 0,note,ni= 1.45*10 10 cm -3 Φ F = 0.46V *10 2*(1.6*10 )*(11.7*8.85*10 *8*10 γ = -14 ± 6 = *8.85*10 6*10 V t = *( ) = 0.68 ox A 26/41

27 onideal characteristics Velocity saturation hannel length modulation Body effect Threshold Variations Parasitic Resistances Subthreshold onduction Hot-carrier effects Latchup Process variations 27/41

28 Threshold Variations V T V T Long-channel threshold Low V S threshold Threshold as a function of the length (for low V S ) L drain-induced barrier lowering-ibl rain-induced barrier lowering (for low L) 28/41

29 Hot-carrier effects evice dimensions have been scaled down continuously, while power supply and the operating voltages have not scaled accordingly Electron become hot which lead to a long-term reliability problem 29/41

30 onideal characteristics Velocity saturation hannel length modulation Body effect Threshold Variations Parasitic Resistances Subthreshold onduction Hot-carrier effects Latchup Process variations 30/41

31 Sub-Threshold onduction Linear region ln(i ) (A) Subthreshold exponential region V T V GS (V) 31/41

32 I (A) Sub-Threshold onduction Quadratic Linear The Slope Factor I ~ I 0 e qvgs nkt, n 1 ox S is VGS for I 2 /I 1 = Exponential V T V GS (V) Typical values for S: mv/decade 32/41

33 onideal characteristics Velocity saturation hannel length modulation Body effect Threshold Variations Parasitic Resistances Subthreshold onduction Junction Leakage Latchup Process variations 33/41

34 Junction leakage Is depends on doping levels and on the area and perimeter of the diffusion region V d is the diode voltage(v sb and V db ) Generally in the fA/um 2 With low threshold voltages, subthreshold conduction far exceeds junction leakage I d = I s (e V v d T -1) 34/41

35 onideal characteristics Velocity saturation hannel length modulation Body effect Threshold Variations Parasitic Resistances Subthreshold onduction Junction Leakage Latchup Process variations 35/41

36 Latchup External voltages can ring below G or above V 36/41

37 Tunneling There is a finite probability that carriers will tunnel through the gate oxide Gate leakage current flowing into the gate The probability of tunneling drops off exponentially with oxide thickness 37/41

38 Temperature dependence arrier mobility decreases with temperature Magnitude of the threshold voltage decrease with temperature Junction leakage increases with temperature 38/41

39 onideal characteristics Velocity saturation hannel length modulation Body effect Threshold Variations Parasitic Resistances Subthreshold onduction Junction Leakage Latchup Process variations 39/41

40 Process variations Variations in the process parameters Impurity concentration densities,oxide thicknesses,iffusion depths Sheet resistances, threshold voltage diverging. Variations in the dimensions of the devices eviations in the W/L ratios Tradeoff between economic and yield 40/41

41 V t trend Low V t? High V t? Some questions Low for high speed, high for low leakage V High voltage result in fast transistor? velocity saturation limit elay Two nmos in series deliver half the current of a single nmos of the same width? Velocity saturation benefit 41/41

42 Summary of general MOSFET scaling trends 42/41

43 Is there life after MOS? 43/41

44 outlook opper has replaced aluminum as interconnect material Low-permittivity interlevel dielectrics are replacing silicon dioxide High-permittivity gate dielectrics to replace silicon dioxide Strained silicon and SiGe technology Metal gates bound to come back Silicon-on-insulator (SOI) technology The search for new device topologies 44/41

45 opper has replaced aluminum as interconnect material The search for a lower-resistivity conductor and a lowerpermittivity interlevel dielectric has prompted industry to replace Al and SiO2 with new materials 45/41

46 opper has replaced aluminum as interconnect material measurements indicated that the effective resistance of u interconnect was 30% to 45% lower than that of traditional Al alloys. u also supports significantly higher current densities. In electromigration tests conducted by IBM, reliability was found to improve by more than two orders of magnitude. 46/41

47 Low-permittivity interlevel dielectrics are replacing silicon dioxide Intel s 65 nm process combined up to eight levels of copper interconnect with a low-permittivity carbon-doped oxide (O) IL (r = 2.9). Tungsten plugs are used for contacts to poly and diffusion. Metal pitches increase gradually from bottom to top igital for optimum I density vs. performance. 47/41

48 High-permittivity gate dielectrics to replace silicon dioxide Intel reports that 45 nm MOSFETs with a Hafniumbased oxide provide either a 25% increase in driveability at the same subthreshold conduction or more than fivefold reduction in leakage for the same drive current when compared to 65 nm transistors with their traditional gate stacks. At the same time, gate oxide tunneling has been reduced by more than a factor of ten A material of low permittivity is desirable for interlevel dielectrics where the lowest possible parasitic capacitances are being sought. Exactly the opposite is true for the gate dielectric in order to minimize gate leakage while maximizing MOSFET drivability and, hence, the switching speed of logic circuits. 48/41

49 Strained silicon and SiGe technology Electron mobility in Si augments when the crystal lattice is subjected to tensile stress, whereas compressive stress tends to improve hole mobility 49/41

50 Metal gates bound to come back A number of undesirable phenomena are associated with polysilicon as a gate material 50/41

51 Silicon-on-insulator (SOI) technology The inherent electrical insulation of MOSFETs does away with the need for wells. o parasitic BJTs and, no exposure to latch-up. o need for body ties and, superior layout density. Reduced sensitivity to radiation effects and higher operating temperatures. The poor thermal conductivity of the insulating layer impedes heat removal. 51/41

52 ew devices In a planar double-gate device (G-MOSFET), a horizontal inversion channel is sandwiched between a pair of electrically connected gate electrodes in such a way as to steer the channel from both sides at the same time The search for better semiconductor materials Vertical integration 52/41

53 The search for new device topologies on-mos data storage Phase-change RAM (PRAM) Ferroelectric RAM (FeRAM) Magnetic RAM (MRAM) 53/41

54 The search for new device topologies on-mos data processing arbon nanotubes Philip G. ollins and Phaedon Avouris. anotubes for Electronics. Scientific American, 283(48):38 45, ecember anojunctions Yu Huang et al. Logic Gates and omputation from Assembled anowire Building Blocks. Science, 294(5545): , ovember 9, Molecular electronics A. J. Heinrich,. P. Lutz, J. A. Gupta, and. M. Eigler. Molecule ascades. Science,298(5597): , ovember arbon monoxide, two-input sorter, molecular electronics. rossbar logic Philip J. Kuekes, Gregory S. Snider, and R. Stanley Williams. rossbar anocomputers. Scientific American, 293(5):50 55, ovember /41

55 The search for new device topologies on-mos data processing Magnetic flux quantum device arren K. Brock, Elie K. Track, and John M. Rowell. Superconductor Is: the 100-GHz second generation. IEEE Spectrum, 37(12):40 46, September Quantum cellular arrays John Baliga. QA evices may take over when MOS is done. Semiconductor International, 22(12):48, October Quantum devices Ralph avin and Victor Zhirnov. Generic device abstractions for information processing technologies. Solid-State Electronics, 50(4): , /41