ELEN0037 Microelectronic IC Design. Prof. Dr. Michael Kraft

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1 ELEN0037 Microelectronic IC Design Prof. Dr. Michael Kraft

2 Lecture 2: Technological Aspects Technology Passive components Active components CMOS Process Basic Layout Scaling

solution poly-gate aluminum membrane passivation n-well n +

3 CMOS Technology Integrated capacitive pressure sensor on 8 wafer using surface micromachining Integrated single chip solution poly-gate aluminum membrane passivation n-well n + - area PMOS NMOS capacitor EEPROM pressure sensor p + - area

4 Passive Components Passive components: Resistors Diffused/implanted resistors Polysilicon resistors Capacitors Aluminium SiO 2 n + p - Substrate n+ diffusion resistor Source: Allen, Holberg, CMOS Analog Circuit Design

5 Fabrication n+ Diffusion Resistor Fabrication process Mask layout n+ - Implantation Aluminium SiO 2 n + p-substrate p - Substrate Diffusion Resistor: Source/Drain diffusion Etch holes n+ p - Substrate Oxide Aluminium n+ p - Substrate

6 n+ Diffusion Resistor Specific conductivity q( n p) Resistance n p n q n q N R = 1 L σ A = 1 L σ X j W 1 L R = qμ n N D X j W 1 R = = Square Resistance qμ n N D X j p n n D σ: specific conductivity μ n, μ p : charge mobility X j : p-n junction depth n,p: charge concentration L : Geometry factor W N D, N A : donor, acceptor concentration Aluminium SiO 2 n + L p-substrate X j A

7 n+ Diffusion Resistor Specific conductivity q( n p) Resistance n p n q n q N R = 1 L σ A = 1 L σ X j W 1 L R = qμ n N D X j W 1 R = = Square Resistance qμ n N D X j p n n D X σ: specific conductivity μ n, μ p : charge mobility X j : p-n junction depth n,p: charge concentration L : Geometry factor W N D, N A : donor, acceptor concentration Square resistance only depends on process parameters L=W R = R Resistors are specified as multiples of their square resistance L = 7W j A L R W R = 7R

8 n+ Diffusion Resistor Typical values for R : Drain-source regions: W/ N-well: W/ Absolute values for diffusion resistors N D, X j, μ n depend on process parameter Diffusion concentration Implantation dose Diffusion temperature Diffusion time etc W, L depend on lithography, etch process, lateral diffusion, etc Edge definition has tolerance of ΔL, ΔW 0.1μm high tolerance for absolute values of resistance, 10-50% For high resistance values, large areas are required

9 Electrical Equivalent Model A R R K, A 0 R K, B B Aluminium SiO 2 n + p-substrate Substrat Contact resistances (R k ) add to resistance value Parasitic diode (pn-junction) to substrate leakage currents, voltage dependent depletion layer capacitance,

10 Resistor Matching How accurate can a resistor ratio be fabricated Example: R 2 = 2 R 1 R N X L W LW R N X L W LW 1 D2 j 2 n D1 j1 n N X N X L L D2 j 2 n2 D1 j1 n1 W W Depend on the process, so should be (pretty) equal across a wafer Depend on the geometry L 1 R 1 W 1 L 2 R 2 W 2 If the resistors are fabbed in the same process, and are close together process tolerances cancel out! with good layout the matching can be better than 1 for circuit design better use ratios!

11 Voltage Dependence Diffusion Resistance Depletion zone width, W n depends on junction reverse voltage bias, V pn + W n X i V pn - P-Substrat n + X i f ( V pn ) W n = 2ε q N A + N D N A N D V bi V pn Xi( Vpn) X i ( Vpn 0) Wn ( Vpn) Resistance increases with junction reverse voltage bias

12 Example m X m V V W m V W V V cm N cm N m X i pn n SP n bi D A i ) 10 ( ) ( (0) R R X X i i

13 Voltage Coefficient Diffusion Resistance 1 1 R V R V Voltage dependency increases with: Lower doping Higher square resistance Thinner layers Typical values n+ implantation: 20 W/ 100ppm/V p+ implantation: 100 W/ 1100ppm/V n- Implantation: 8 kw/ ppm/v 160 ppm / V

14 Temperature Dependency Diffusion Resistance Effective mobility is temperature dependent f (T ) 0 T T 0 m ; m f ( N D, N A ) R R 0 T T 0 m 1 R R T m T TK R m depends on various scattering mechanisms Temperature dependence decreases for higher doping levels Typical values: n+ implantation: 20 W/ 1500ppm/K n- implantation: 8 kw/ 8000ppm/K

15 Polysilicon Resistors

16 Polysilicon Resistors highly doped polycrystalline silicon used a Gate material, interconnects Poly-Si Aluminium Spacer-oxide Field oxide p - Substrate Electrical equivalent circuit: R R K, A 0 R K, B ( typ.10 cm 20 3 doping concentration ) Current is nonlinear due to grain boundaries I I sinh s 2 elk V ktl C P C P Substrate L: resistor length L k : grain length, typ nm Relatively good linearity

17 Voltage Dependency Polysilicon Resistors 1 R 1 R dr dv 1 3 dl dv 1 V l s elk 2kTL elk cosh 2kTL elkv 1 coth 2kTL 2 V elk V 2kTL elkv 2kTL Long resistors have better linearity Typ. Value ppm/v e.g. W=25 m, L=2500 m 30 ppm/v

18 Temperature Dependency Polysilicon Resistors 1 R dr dt 1 T 1 elkv 2kTL coth elkv 2kTL 1 3T elkv 2kTL 2 Long resistors have lower temperature dependency Typ. Value ppm/k e.g. L=300 m, V=2 V 200 ppm/k

Capacitors CMOS technology: High quality, thin gate oxide layers are available Using MOSFET, one can realize switches with low losses Using MOSFET, one

19 Capacitors CMOS technology: High quality, thin gate oxide layers are available Using MOSFET, one can realize switches with low losses Using MOSFET, one can read-out stored voltages without (almost) losses SiO 2 Gate SiO 2 Alu Polysilicon Feldoxid Field oxide Field Feldoxid oxide p- substrate n + Implantation

20 Poly Diffusion Capacitor CMOS technology: High quality, thin gate oxide layers are available Thickness nm (Field oxide about factor 10 thicker) Using MOSFET, one can realize switches with low losses Using MOSFET, one can read-out stored voltages without (almost) losses Aluminium Capacitor-Oxide Poly A Electrical lumped parameter model B C 0 n + n + t OX C PA C PB p-substrate Field oxide C O 0 t r, SiO 2 OX A C ox Substrat A C ox WL

21 Poly Diffusion Capacitor C* depends on the process only Typical values 500 pf/mm nf/mm 2 Small temperature and voltage dependency Absolute accuracy 10%..20% Matched pairs accuracy < 0.1% Disadvantage: diode to substrate 1 C 1 C dc 20 ppm / K dt dc 7 ppm / V dv Aluminium Capacitor-Oxide Poly n + n + p-substrate t OX Field oxide

22 Poly-Poly Capacitor Poly Top Plate Poly Bottom Plate Field oxide p- Substrate Capacitor oxide

23 Poly-Poly Capacitor Capacitor-Oxide Poly 2 Spacer oxide p-substrate Poly 1 Fieldoxide A C 0 B Electrical lumped parameter model C P1 C P2 C 0 0 t r, Sio 2 OX A C ox A C ox W L

24 Poly-Poly Capacitor Absolute Value Source of tolerances 1. Edge uncertainty due to tolerances in Lithography Etching W+ and L+ Area A = WL, circumference U = 2 (W+L) A` W L WL W L U A A 2 A A U A 2A 2 U A 2 minimal error for minimum ratio U to A quadratic layout (best spherical) 2. oxide thickness Process dependent 2 2 W L 2

25 Capacitors: Matching Area and circumference have to adjusted Required capacitor value build up from quadratic unit capacitors Oxide thickness changes across a wafer (gradient) Common centroid layout example: parasitic capacitors Electrodes to substrate Interconnect Fringe field and stray capacitors Can be in the same order as C 0 Circuit should be insensitive C 0 0 t r, SiO 2 OX 1 C 2 1 C A C ox A C ox W L 1 C C 2 2

26 Precision of Passive Components Diffusion Resistor Thinfilm Resistor Capacitor Absolute % 1 % % Matching % (9 10 bit) % (9 12 bit) % (7 11 bit) Temperature Coefficient Voltage coefficient 2000 ppm/k 100 ppm/k 25 ppm/k ( ) ppm/v 1 ppm/v ppm/v

27 a) n - well MOSFET Fabrication Well oxide n - well p - substrate n - Wanne well b) Aktive areas Field oxide Gate oxide n - well p - substrate Feldoxid Field oxide

28 c) Poly silicon MOSFET Fabrication Poly - Si Poly - Si mask n - well p - substrate Polysilizium silicon d) PMOS - Drain / Source p + p + n - Well p - Substrate p - MOS Transistor p + - Maske mask

29 e) NMOS - Drain / Source MOSFET Fabrication n + n + p + p + n - Well p - Substrate n + - Mask f) Contacts n - MOS Transistor n + n + p + p + n - Well p - Substrate Kontaktl ö Contact cher holes

30 MOSFET Fabrication g) Metal n + n + p + p + n-well P-substrate Contact holes

31 MOSFET Structure

32 Layout Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain Set by minimum width of polysilicon Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules Express rules in terms of l = f/2 E.g. l = 0.3 m in 0.6 m process

33 Layout Design Rules

34 Design Rules Summary Metal and diffusion have minimum width and spacing of 4l Contacts are 2l x 2l and must be surrounded by 1l on the layers above and below Polysilicon uses a width of 2l Polysilicon overlaps diffusions by 2l where a transistor is desired and has spacing or 1l away where no transistor is desired Polysilicon and contacts have a spacing of 3l from other polysilicon or contacts N-well surrounds pmos transistors by 6l and avoid nmos transistors by 6l

35 Gate Layout Layout can be very time consuming Design gates to fit together nicely Build a library of standard cells Standard cell design methodology VDD and GND should abut (standard height) Adjacent gates should satisfy design rules nmos at bottom and pmos at top All gates include well and substrate contacts

36 Inverter Layout Transistor dimensions specified as W / L ratio Minimum size is 4l / 2l, sometimes called 1 unit In f = 0.6 m process, this is 1.2 m wide, 0.6 m long

37 Example: Inverter Standard Cell Layout

38 Example: 3-input NAND Standard Cell Layout Horizontal n-diffusion and p- diffusion strips Vertical polysilicon gates Metal1 VDD rail at top Metal1 GND rail at bottom 32 l by 40 l

39 Stick Diagrams Stick diagrams help plan layout quickly Need not be to scale Draw with color pencils or dry-erase markers

40 Wiring Tracks A wiring track is the space required for a wire 4 l width, 4 l spacing from neighbor = 8 l pitch Transistors also consume one wiring track

41 Well spacing Wells must surround transistors by 6 l Implies 12 l between opposite transistor flavors Leaves room for one wire track

42 Area Estimation Estimate area by counting wiring tracks Multiply by 8 to express in l

43 Scaling The simplest and most common scaling approach is constant field scaling. The dimensions are scaled in the horizontal & vertical directions, and proportionally increasing the substrate doping by a factor l, to keep the electric field distribution unchanged. One of the major changes in a short-channel device is that electric field in the channel region becomes two-dimensional due to the influence of the drain potential. The substrate doping has to be increased to decrease the depletion width (following from Poisson s equation). Small transistors have various undesired effects such as gate oxide degeneration due to hot electrons, threshold voltage shift, gate-induced drain leakage, drain-induced barrier lowering (DIBL). Changes in the fabrication flow have to be introduced to mitigate these unwanted effects, and keep short-channel devices operational.

44 Constant Field Scaling t OX Parameter Factor Dimensions (W, L, t OX, ) 1/l Capacitors 1/l Voltages 1/l Currents 1/l Power 1/l 2 Noise density (kt/c) l SNR 1/l 3

45 Constant Field Scaling Parameter Scaling Factor Device Dimensions W, L, t OX 1/l Capacitance C 1/l Line Resistance l Contact Resistance l 2 Line Delay 1 Voltage V 1/l Current I 1/l Power P 1/l 2 "On"-Resistance 1 Delay T = R on C 1/l Power-Delay Product 1/l 3 Transconductance g m 1 Noise Power (kt/c) l SNR 1/l 3

46 Intel 20nm Technology

VLSI VLSI CIRCUIT DESIGN PROCESSES P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT

VLSI VLSI CIRCUIT DESIGN PROCESSES P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) SYLLABUS UNIT II VLSI CIRCUIT DESIGN PROCESSES: VLSI Design Flow, MOS Layers, Stick Diagrams, Design Rules and Layout, 2 m CMOS Design