EECS130 Integrated Circuit Devices

Transcription

1 EECS130 Integrated Circuit Devices Professor Ali Javey 10/30/2007 MOSFETs Lecture 4 Reading: Chapter 17, 19

2 Announcements The next HW set is due on Thursday. Midterm 2 is next week!!!!

3 Threshold and Subthreshold

4 Subthreshold Current The leakage current that flows at V g <V t is called the subthreshold current. Previously we had assumed that current is zero, but in reality that s not the case. I ds (μ A/μm) Intel, T. Ghani et al., IEDM nm technology. Gate length: 45nm for NMOS, 50nm for PMOS V gs The current at V gs =0 and V ds =V dd is called I off.

5 Subthreshold current n s (surface inversion carrier concentration) n s e qϕs/kt ϕ S Ef V g ϕ s (surface potential) varies with V g through a capacitor network C ox C dep V g ψ S dϕs Coxe 1 = = dv C + C η g oxe dep In subthreshold, ϕ s = constant +V g /η

6 Subthreshold Leakage Current I ds n s e ( constant + V ) / kt qϕ / kt q /η /ηkt s e gs e qv gs C ox V G I ds qv gs /ηkt e C dep ϕ s η = 1 + C dep C oxe Subthreshold current changes 10x for η 60mV change in V g. Reminder: 60mV is (ln10) kt/q Subthreshold swing, S : the change in V gs corresponding to 10x change in subthreshold current. S = η 60mV, typically mV

7 Subthreshold Leakage Current Practical definition of V t : the V gs at which I ds = 100nA W/L => W q( Vg Vt )/ ηkt W ( Vg Vt )/ S Isubthresho ld ( na) 100 e = L L Log (I ds ) 100 W/L(nA) I off V ds =V dd I off (na) = W L V t is determined only by V t and subthreshold swing. / S V t V gs

8 Subthreshold Swing (S) Smaller S is desirable (lower I off for a given V t ). Minimum possible value of S is 60mV/dec. What are 3 ways to lower swing? Limitations C S 60mV 1 + C = oxe dep

9 Subthreshold Swing (S) S = Theoretical limit for S for a MOSFET is 60 mv/decade. New device concepts are being explored to make new generation of transistors that beat the 60 mv/decade limit.

10 room temperature Velocity Saturation v = 1 μ se E + E sat E << E sat : v = μ s E E >> E sat : v = μ s E sat velocity saturation has large and deleterious effect on the I on of MOSFETS

11 Velocity Saturation where v sat is the carrier saturation velocity

12 Measured MOSFET IV Velocity Saturation Ids (ma/μm) L = 0.15 μm V t = 0.4 V V gs = 2.5V V gs = 2.0V V gs = 1.5V V gs = 1.0V V ds (V) With velocity saturation I ds (μa/μm) L = 2.0 μm V gs = 2.5V V ds (V) V gs = 2.0V V gs = 1.5V V gs = 1.0V What is the main difference between the V g dependences of the longand short-channel length IV curves? V t = 0.7 V Without velocity saturation

13 Ballistic Devices If the channel is short enough (below the mean free path length scales), then the carriers can travel from source to drain without going through any significant scattering events. This is called ballistic transport. Carriers can often gain an average velocity over v sat. This phenomena is known as velocity overshoot. State-of-the-art Si MOSFETs are operating at ~40% the ballistic limit.

14 Series Resistance of S/D So far we have been assuming that there is no potential drop in S/D. For miniaturized/scaled devices that is not the case and the parasitic resistance of S/D plays an important role in the IV characteristics.

15 S/D Series Resistance Series resistance is highly undesirable and can cause severe performance degradation.

16 MOSFET Technology Scaling Technology Scaling Small is Beautiful YEAR Technology Generation 0.5 μm 0.35 μm 0.25 μm 0.18 μm 0.13 μm 90 nm 65 nm 45 nm New technology node every three years or so. Defined by minimum metal line width. All feature sizes, e.g. gate length, are ~70% of previous node.

17 MOSFET Technology Scaling

18 V t roll-off: V t decreases with decreasing L g. It determines the minimum acceptable L g because I off is too large if V t becomes too small. V t Roll-off K. Goto et al., (Fujitsu) IEDM nm technology. EOT=1.2nm, V dd =1V

19 Why Does V t Decrease with L? Potential Barrier Concept Long Channel V gs =0V Short Channel V gs =0V V g =0V E c N + Source V ds N + Drain V g =V t ~0.2V V gs =V t-long V gs =V t-short When L is small, smaller V g is needed to reduce the barrier to 0.2V, i.e. V t is smaller. V t roll-off is greater for shorter L

20 Energy-Band Diagram from Source to Drain L dependence source/channel barrier long channel V ds short channel V ds dependence long channel log(i ds ) V ds =0 V ds short channel V ds =V dd V ds =V dd V gs

21 Reducing the Gate Insulator Thickness and T oxe Oxide thickness has been reduced over the years from 300nm to 1.2nm. Why reduce oxide thickness? Larger C ox to raise I on Reduce subthreshold swing Control V t roll-off Thinner is better. However, if the oxide is too thin Breakdown due to high electric field Leakage current

22 Tunneling Leakage Current For SiO 2 films thinner than 1.5nm, tunneling leakage current has become the limiting factor. HfO 2 has several orders lower leakage for the same EOT.

23 Replacing SiO 2 with HfO 2 ---High-k Dielectric (After W. Tsai et al., IEDM 03) HfO 2 has a relative dielectric constant (k) of ~24, six times large than that of SiO 2. For the same EOT, the HfO 2 film presents a much thicker (albeit a lower) tunneling barrier to the electrons and holes. Toxe can be further reduced by introducing metal-gate technology since the poly-depletion effect is eliminated.

24 Challenges of High-K Technology The challenges of high-k dielectrics are chemical reactions between them and the silicon substrate and gate, lower surface mobility than the Si/SiO 2 system too low a V t for P-channel MOSFET (as if there is positive charge in the high-k dielectric). A thin SiO 2 interfacial layer may be inserted between Si-substrate and high-k film.