# Lecture #27. The Short Channel Effect (SCE)

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1 Lecture #27 ANNOUNCEMENTS Design Project: Your BJT design should meet the performance specifications to within 10% at both 300K and 360K. ( β dc > 45, f T > 18 GHz, V A > 9 V and V punchthrough > 9 V ) OUTLINE Short channel effect Drain-induced barrier lowering Excess current effects Parasitic source/drain resistance EE130 Lecture 26, Slide 1 The Short Channel Effect (SCE) V T roll-off V T decreases with L Effect is exacerbated by high values of V DS This is undesirable (i.e. we want to minimize it!) because circuit designers would like V T to be invariant with transistor dimensions and biasing conditions EE130 Lecture 26, Slide 2

2 Qualitative Explanation of SCE Before an inversion layer forms beneath the gate, the surface of the Si underneath the gate must be depleted (to a depth W dm ) The source & drain pn junctions assist in depleting the Si underneath the gate Portions of the depletion charge in the channel region are balanced by charge in S/D regions, rather than by charge on the gate less gate charge is required to reach inversion (i.e. V T decreases) EE130 Lecture 26, Slide 3 The smaller the L, the greater percentage of charge balanced by the S/D pn junctions: depletion charge supported by gate (simplified analysis) n + n + p V G r j depletion region Large L: Small L: S D S D Depletion charge supported by S/D Depletion charge supported by S/D EE130 Lecture 26, Slide 4

3 First-Order Analysis of SCE The gate supports the depletion charge in the trapezoidal region. This is smaller than the rectangular depletion region underneath the gate, by the factor L + L 1 2L This is the factor by which the depletion charge Q dep is reduced from the ideal One can deduce from simple 2W dm geometric analysis that L = L 2rj 1+ 1 rj EE130 Lecture 26, Slide 5 W dm V T V T Roll-Off: First-Order Model qn AW r dm j 2Wdm V = + T ( long channel ) VT 1 1 C oxe L rj Minimize V T by reducing T oxe W dm reducing r j increasing N A (trade-offs: degraded m, µ) MOSFET vertical dimensions should be scaled along with horizontal dimensions! EE130 Lecture 26, Slide 6

4 Source and Drain Structure To minimize SCE, we want shallow (small r j ) S/D regions -- but the parasitic resistance of these regions will increase when r j is reduced. R, R ρ / Wr source drain where ρ = resistivity of the S/D regions Shallow S/D extensions may be used to effectively reduce r j without increasing the S/D sheet resistance too much j EE130 Lecture 26, Slide 7 Electric Field Along Channel The lateral electric field peaks at the drain. E peak can be as high as 10 6 V/cm High E-field causes several problems: impact ionization substrate current damage to gate-oxide interface and bulk EE130 Lecture 26, Slide 8

5 Lightly Doped Drain Structure Lower pn junction doping results in lower peak E-field Hot-carrier effects reduced Series resistance increased EE130 Lecture 26, Slide 9 Parasitic Source-Drain Resistance contact metal dielectric spacer G gate S R s R d D oxide channel I Dsat0 IfI Dsat0 V GS V T, I Dsat = I Dsat0Rs 1+ ( VGS VT ) I Dsat is reduced by about 15% in a 0.1µm MOSFET. V Dsat = V Dsat0 + I Dsat (R s + R d ) CoSi 2 or TiSi 2 N + source or drain EE130 Lecture 26, Slide 10

6 Drain Induced Barrier Lowering (DIBL) As the source & drain get closer, they become electrostatically coupled, so that the drain bias can affect the potential barrier to carrier flow at the source junction subthreshold current increases. EE130 Lecture 26, Slide 11 Punchthrough Excess Current Effects EE130 Lecture 26, Slide 12

7 Parasitic BJT action EE130 Lecture 26, Slide 13 Summary: MOSFET OFF State vs. ON State Sub-threshold regime (V GS < V T ): I DS is limited by the rate at which carriers diffuse across the source pn junction Subthreshold swing S, DIBL are issues ON state (V GS > V T ): I DS is limited by the rate at which carriers drift across the channel Punchthrough and parasitic BJT effects are of concern, particularly at high drain bias I Dsat increases rapidly with V DS Parasitic series resistances reduce drive current source resistance R S reduces effective V GS source and drain resistances R S and R D reduce effective V DS EE130 Lecture 26, Slide 14

8 EE130 Lecture 26, Slide 15

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