ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals


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1 University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2016 Final Friday, May 6 5 Problems with point weightings shown. All 5 problems must be completed. Calculators allowed. Closed book = No text or notes allowed. Clearly label all final answers. Name: 1
2 University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2016 Formulas and Data Friday, May 6th Physical Constants: n i = intrinsic concentration (undoped) silicon = cm 300 K k = Boltzman s constant = J/ K q = electronic charge = C 1 angstrom = 10 8 cm ɛ Si = permittivity of Si = F/cm ɛ SiO2 = ɛ ox = permittivity of SiO 2 = F/cm MOS Transistor IV Characteristics: nmos: pmos: V GS V DS Mode I DS ) V GS V T h e nkt /q ( 1 e V DS kt /q ) (1 + λv DS ) V T h Subthreshold ( I W S L > V T h < V GS V T h Resistive k n2 (2(V GS V T h )V DS VDS)(1 2 + λv DS ) V GS V T h Saturation k n2 (V GS V T h ) 2 (1 + λv DS ) k n = µ n C ox W n L n V GS V DS Mode I DS ) V GS V T h e nkt /q ( 1 e V DS kt /q ) (1 + λv DS ) V T h Subthreshold ( I W S L < V T h > V GS V T h Resistive k n2 (2(V GS V T h )V DS VDS)(1 2 + λv DS ) V GS V T h Saturation k n2 (V GS V T h ) 2 (1 + λv DS ) k p = µ p C ox W p L p Threshold Voltage: V T h = V T 0 + γ ( 2φ F + V SB 2φ F ) (psub) φ F = kt ln n i q N A γ = 2ɛ Si qn A C ox and (nsub) φ F = kt q ln N D ni 2
3 CMOS Capacitors: C ox = ɛox t ox C O = C GSO = C GDO = C ox W L D MOS Gate Capacitance: MOS Diffusion Capacitance: C diff = C db = A D C j0 + P D C j0sw A D = Area of diffusion region P D = Perimeter of diffusion region Static/Dynamic Characteristics of Gates: V 50% = 1 2 (V OL + V OH ) τ P HL = time for output voltage to fall from V OH to V 50% τ P LH = time for output voltage to rise from V OL to V 50% τ P = τ P HL+τ P LH 2 Average Current Delay Model: τ P HL = C load V HL I avg,hl = C load(v OH V 50% ) I avg,hl τ P LH = C load V LH I avg,lh = C load(v 50% V OL ) I avg,lh Firstorder RC Delay Model: τ P HL = 0.69 C load R P D τ P LH = 0.69 C load R P U Power Equations: P tot = P dyn + P SC + P stat P dyn = dynamic power = a ( ) 1 Cload V 2 f 2 P SC = short circuit power = ac SC V 2 f P stat = static power = V I stat where a=acitivity factor, f=switching frequency 3
4 1. (30 pts) Consider the simple 2input multiplexer implementation using pass transistors and CMOS inverters: All transistors W=L=1. The unit resistance of an nmos with W=L=1 is R un. The unit resistance of a pmos with W=L=1 is R up = R un. The gate capacitance and diffusion capacitance of a unit nmos and pmos are C g and C diff respectively. Assume inputs are driven by R un drive with 2C diff self load. Using the firstorder RC model, report delay from this R un input driver driving the inputs through to the output of this circuit driving a 4C g load. Assume all inputs arrive at the same time, and give answer in terms of R un, C diff, and C g. Show work for partial credit. 4
5 Page Left Intentionally Blank 5
6 2. (20 pts) Following is a dynamic DLatch with its corresponding symbol. Using the dynamic DLatch above, a failed attempt to implement the least significant bit of a counter (toggles logic value on every positive edge of clock cycle), and a waveform showing how it does perform Circuit Behavior CLK toggle 0.6 V e09 2e09 3e09 4e09 s (a) What is going wrong with this circuit? (qualitative answer expected) (b) How would you modify the circuit to achieve correct operation? 6
7 3. (20 pts) Following is an attempt to compute A*B+C in domino logic that does not work correctly. (a) What does the circuit currently compute? (b) What is wrong with this circuit? (Qualitative explanation of the phenomenon.) 7
8 (c) How would you fix this circuit? (draw revised correct circuit) 8
9 4. (20 pts) SRAM memory array. Assume we have a 5transistor SRAM cell consisting of two inverters in feedback storing the bit value with one access transistor for both the read and write operations. The memory cell in the figure below is used to create a memory array with d rows and w columns (d words of w bits each). (a) What is the capacitance of the bit line, BL, in terms of access transistor width W access, d, and C diff? (b) Assume bit line, BL, is precharged to V dd prior to a read operation. During the read operation, what is the delay of the memory cell driving BL in terms of W access, d, C diff, R un, and W 1. 9
10 (c) What is the capacitance of the word line, WL in terms of W access, w, and C g? (d) Assuming word line, WL, is driven by an inverter with transistor sizing W n = W p = W wldrive, what is the delay driving WL in terms of W wldrive, W access, w, C diff, C g, and R un? 10
11 5. (10 pts) Given below is the 1T DRAM cell with sample waveforms for writing a 1 and reading the cell in sequence. Describe the operation of the cell for the write/read sequence shown. Give details of what happens to the bit line (BL) and word line (WL). Discuss any design considerations that must be accounted for with this cell for long term operation. Waveform X is the voltage on storage capacitor C S. 11
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