CMOS Transistors, Gates, and Wires


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1 CMOS Transistors, Gates, and Wires Should the hardware abstraction layers make today s lecture irrelevant? pplication R P C W / R W C W / Complex Digital Systems Christopher atten February 5, 006 lgorithm Guarded tomic ctions RegisterTransfer Level Gates Circuits Devices Physics Previous Two Lectures Today s Lecture Spring 006 L04 CMOS Transistors, Gates, and Wires Should the hardware abstraction layers make today s lecture irrelevant? CMOS Transistors, Gates, and Wires pplication lgorithm Guarded tomic ctions Physical design issues are increasingly pushing their way up the abstraction layers Transistors Wires Gates RegisterTransfer Level Gates Circuits Devices It is essential for modern digital designers to have some intuition about the lower level physical design issues input 0 input output Physics Spring 006 L04 CMOS Transistors, Gates, and Wires Spring 006 L04 CMOS Transistors, Gates, and Wires 4
2 Metal OxideSemiconductor FieldEffect (MOSFET) Transistor Overview of operation of a NMOS transistor Gate Inversion happens here V GS Gate V DS V DS D Source diffusion E h Drain diffusion Source diffusion I D Drain diffusion V GS G S E v bulk bulk I D I D lg(i D ) V INVERSION: sufficiently strong vertical field will attract enough electrons to the surface to create a conducting ntype channel between the source and drain. CONDUCTION: If a channel exists, a horizontal field will cause a drift current from the drain to the source. V DS V t V GS V t V GS time Spring 006 L04 CMOS Transistors, Gates, and Wires Spring 006 L04 CMOS Transistors, Gates, and Wires 6 Key qualitative characteristics of MOSFET transistors CMOS Transistors, Gates, and Wires Width Transistors Gates Reff Wires Length Threshold voltage sets when transistor turns on also impacts leakage I DS is proportional to mobility x (W/L) NMOS mobility > PMOS mobility > N < P (assume mobility ratio is ) Increase W Increase I Decrease Increase L Decrease I Increase proportional to ( W x L ) and proportional to W input 0 input output Spring 006 L04 CMOS Transistors, Gates, and Wires Spring 006 L04 CMOS Transistors, Gates, and Wires 8
3 The most basic CMOS gate is an inverter The most basic CMOS gate is an inverter Let s make the following assumptions V W P /L P W N /L N α α. ll transistors are minimum length. ll gates should have equal rise/fall times. Since PMOS are twice as slow as NMOS they must be twice as wide to have the same effective resistance 3. Normalize all transistor widths to minimum width NMOS W P /L P W N /L N α α Y PMOS NMOS GND Spring 006 L04 CMOS Transistors, Gates, and Wires Spring 006 L04 CMOS Transistors, Gates, and Wires 0 simple RC model for the inverter can provide significant insight simple RC model for the inverter can provide significant insight,n,p,n +,P,N +,P Spring 006 L04 CMOS Transistors, Gates, and Wires Spring 006 L04 CMOS Transistors, Gates, and Wires
4 simple RC model for the inverter can provide significant insight The most basic CMOS gate is an inverter 0 Charge RC Time Constant x ( + ) Discharge RC Time Constant x ( + ) Spring 006 L04 CMOS Transistors, Gates, and Wires Spring 006 L04 CMOS Transistors, Gates, and Wires 4 Larger gates are faster since they decrease (but they also increase!) Simple RC model can also yield intuition on energy consumption of inverter Process gen 0.5µm Supply voltage 5V Min width NMOS 0.5µm Param Value Units,N /µm.4,p /µm.40,n /µm.55 (0.5x.4) + (x.40) 3. ff (0.5x.55) + (x.48).6 ff ff T PLH. x (0.83/) x ps T PHL. x (4.93/0.5) x ps 0 Reff E 0 V dv t V dt (C + C )V d T 0 T 0 P(t) dt V L T 0 CV I(t) dt V V (C 0 d + C )dv L T 0 dq dt dt out,p /µm.48,n x µm,p x µm (x.4) + (x.40) 3.66 ff (0.5x.55) + (x.48).6 ff ff T PLH. x (0.83/) x ps T PHL. x (4.93/) x ps During 0 transition, energy CV removed from power supply fter transition, / CV stored in capacitor, the other / CV was dissipated as heat in pullup resistance Ignores the fact that previous gate now must drive a bigger gate capacitance! Spring 006 L04 CMOS Transistors, Gates, and Wires 5 The / CV energy stored in capacitor is dissipated in the pulldown resistance on next 0 transition Spring 006 L04 CMOS Transistors, Gates, and Wires 6
5 Larger gates use slightly more energy, real concern is affect on previous gate Many other types of power consumption in addition to dynamic power Process gen 0.5µm Supply voltage 5V Min width NMOS 0.5µm Param Value Units,N /µm.4 (0.5x.4) + (x.40) 3. ff (0.5x.55) + (x.48).6 ff ff E 0> 5.37 x 5 34fJ,P /µm,n /µm Reff Reff,P /µm.48,n x µm,p x µm (x.4) + (x.40) 3.66 ff (0.5x.55) + (x.48).6 ff ff E 0> 5.9 x 5 48fJ Short Circuit Current Subthreshold Leakage Fast edges keep to <0% of cap charging current pproaching 040% of active power Ignores the fact that previous gate now must drive a bigger gate capacitance! Spring 006 L04 CMOS Transistors, Gates, and Wires 7 Diode Leakage Gate Leakage Usually negligible Was negligible, increasing due to thin gate oxides Spring 006 L04 CMOS Transistors, Gates, and Wires 8 More complicated gates use more transistors in pullup/pulldown networks Series and parallel MOSFET networks provide natural duals of each other V Input 0 Input Input N Pullup network, connects output to V, contains only PMOS V OUT Pulldown network, connects output to GND, contains only NMOS Conducts if 0 Conducts if 0 OR 0 Conducts if 0 ND 0 For every set of input logic values, either pullup or pulldown network makes connection to V or GND If both connected, power rails would be shorted together If neither connected, output would float (tristate logic) Conducts if Conducts if ND Conducts if OR Spring 006 L04 CMOS Transistors, Gates, and Wires Spring 006 L04 CMOS Transistors, Gates, and Wires 0
6 NND and NOR gates illustrate the dual nature of the pullup/pulldown networks Designers can use a methodical approach to build more complex gates NND Gate (.) NOR Gate (+) Goal is to create an logic function We can only implement inverting logic with one CMOS stage Implement pulldown network Write PD f(x, x, K) Use parallel NMOS for OR of inputs Use series NMOS for ND of inputs f (x, x, K) (.) (+) Implement pullup network Write pullup network PU f(x, x, K ) g(x, x, K) Use parallel PMOS for OR of complemented inputs) Use series PMOS for ND of complemented inputs) Spring 006 L04 CMOS Transistors, Gates, and Wires Spring 006 L04 CMOS Transistors, Gates, and Wires Designers can use a methodical approach to build more complex gates CMOS Transistors, Gates, and Wires f ( + ) C Transistors Gates C (+).C PD PU ( ( ( + ) C + ) C + ) + C input 0 Wires output ( ) + C input Spring 006 L04 CMOS Transistors, Gates, and Wires Spring 006 L04 CMOS Transistors, Gates, and Wires 4
7 Wires are an old problem Modern interconnect stacks have six to nine or more metal layers Cray 976 Metal 6 Via 56 Metal 5 Metal 4 IM Cray3 wiring Metal Metal Metal 3 Via  Cray Cray Wiring Spring 006 L04 CMOS Transistors, Gates, and Wires 5 IM CMOS7 process IM 6 layers of copper wiring layer of tungsten local interconnect Spring 006 L04 CMOS Transistors, Gates, and Wires 6 Wire resistance is a function of height, width, and length Height Width Length resistance bulk aluminum bulk copper bulk silver ( length resistivity ) ( height width ) Height (Thickness) fixed in given manufacturing process Resistances quoted as Ω/square TSMC 0.8mm 6 luminum metal layers M Ω/square (0.5 mm x mm wire 60 Ω) M Ω/square (0.5 mm x mm wire 60 Ω).8x08 Ωm.7x08 Ωm.6x08 Ωm Wire capacitance is relative to the substrate and to neighboring wires ε W W Capacitance depends on geometry of surrounding wires and relative permittivity (ε r ) of insulating dielectric silicon dioxide (SiO ) ε r 3.9 silicon flouride (SiF 4 ) ε r 3. SiLK TM polymer ε r.6 S H D H D D Capacitive coupling to neighbors is becoming a serious problem! Spring 006 L04 CMOS Transistors, Gates, and Wires Spring 006 L04 CMOS Transistors, Gates, and Wires 8
8 Wire capacitance is relative to the substrate and to neighboring wires This IM experimental 30nm process includes two metals and two dielectrics ε H ε W D l ε ε D W S H D D Capacitance depends on geometry of surrounding wires and relative permittivity (ε r ) of insulating dielectric silicon dioxide (SiO ) ε r 3.9 silicon flouride (SiF 4 ) ε r 3. SiLK TM polymer ε r.6 Can have different materials between wires and between layers, and also different materials on higher layers Spring 006 L04 CMOS Transistors, Gates, and Wires 9 E. arth, IM Microelectronics Spring 006 L04 CMOS Transistors, Gates, and Wires 30 Distributed RC wire model gives accurate results but is computationally expensive Lumped Π model can provide a quick reasonable approximation R driver R C R C Use PenfieldRubenstein equation to find delay N j i Delay R j Ci i j How does the delay scale with longer wires? Wire delay increases quadratically Edge rate also degrades quadratically R N C N Cload R driver R w C load Delay R driver C w / C w / C w + w ( R + R ) + C driver w C R w is lumped resistance of the wire C w is lumped capacitance Partition half of C w at each end load Spring 006 L04 CMOS Transistors, Gates, and Wires Spring 006 L04 CMOS Transistors, Gates, and Wires 3
9 Estimate the rise time of node using an Relay model Estimate the rise time of node using an Relay model Process gen 0.5µm Supply voltage 5V Min width NMOS 0.5µm 6 Metal wire (50u x 0.50u) Process gen 0.5µm Supply voltage 5V Min width NMOS 0.5µm 6 Metal wire (50u x 0.50u) Param,N / µm Value.4 Units 8 Param,N / µm Value.4 Units 8,P / µm,n / µm,p / µm C,M / µm R P C W / R W C W /,P / µm,n / µm,p / µm C,M / µm How should we buffer up this signal? Should we have a few big stages or many small stages?,m / µm,n x µm,p x µm R M / sq Ω/sq ( 0.5 x.55 ) + ( x.48 ).6 ff (4 x.4 ) + ( 8 x.40 ) 4.88 ff R p 0.83/8.35 kω ( 50 / 0.5 ) x Ω R w C w (( 50 x 0.5 ) x ) + ( 50 x ).4 ff T PLH. x ( 350 x (.4/ ) + ( ) x (.4/ +.6) ) 66ps,M / µm,n x µm,p x µm R M / sq Ω/sq Spring 006 L04 CMOS Transistors, Gates, and Wires Spring 006 L04 CMOS Transistors, Gates, and Wires 34 In deep submicron technologies many predicted an interconnect doomsday Is there really an interconnect doomsday looming? Local wire delay tracks improvement in gate delay Scaling Impact ffect on Resistance ffect on Capacitance Length Decreases Decreases Decrease Width Decreases Increases Decrease Height ~ Constant National Technology Roadmap for Semiconductors, SI, Spring 006 L04 CMOS Transistors, Gates, and Wires 35 R. Ho, K. Mai, M. Horowitz, Proc. of the IEEE, pr Spring 006 L04 CMOS Transistors, Gates, and Wires 36
10 Is there really an interconnect doomsday looming? No doomsday, just one more physical design issue to carefully manage Length Width Scaling Impact ~ Constant Decreases ffect on Resistance Increases ffect on Capacitance Decrease Global wire delay increases relative to wire delay! Height ~ Constant R. Ho, K. Mai, M. Horowitz, Proc. of the IEEE, pr Spring 006 L04 CMOS Transistors, Gates, and Wires 37 National Technology Roadmap for Semiconductors, SI, Spring 006 L04 CMOS Transistors, Gates, and Wires 38 Take away points Simple RC models of CMOS transistors, gates, and wires can provide reasonable insight into the power and delay of circuits methodological approach enables creating static CMOS gates relatively straightforward lthough global wire delay is getting worse relative to gate delay, local wire delay is scaling with gate delay which forces designers to better manage global wires early in the design process Next Lecture: Srini Devadas will be discussing algorithms and issues in synthesis and place+route Spring 006 L04 CMOS Transistors, Gates, and Wires 39
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